anaza3
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programming DE5-net with custom BSP
I am trying to program a DE5-net board with a custom BSP. the BSP is same as the one provided by trasic except that I added a module in the qsys file to read from DRAM some data and write it back to the DRAM(nothing really has to do with opencl module as it collects some other info about DRAM data). The module is tested with DRAM and works fine. I changed the qsys file and set the variable ACL_QSH_COMPILE_CMD for base flow. export ACL_QSH_COMPILE_CMD='quartus_sh --flow compile top -c base' I commented out these line in post-script # Generate fpga.bin used for reprogramming post_message "Generating fpga.bin" if {[catch { call_script_as_function scripts/create_fpga_bin.tcl $revision_name.sof $revision_name.core.rbf $revision_name.periph_hash $revision_name } res]} { post_message -type error "Error in create_fpga_bin.tcl! $res" exit 2 } and also deleted the persona directory. (I concluded I need to go through these steps based on this document(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/ug_aocl_s5_net_platform.pdf) I compiled the output by aoc device/vector_add.cl -board=de5net_a7 -report -v -o bin/vector_add.aocx the compilation generates the project and compiles it and it all finishes successfully. I can see my module is added to the output when I look into the chip planner. However, when I try to program the board: /trojan/tests/vector_add$ aocl program acl0 bin/vector_add.aocx -------------------------------------------------------------------- No programming routine supplied. Please consult your board manufacturer's documentation or support team for information on how to load a new image on to the FPGA. -------------------------------------------------------------------- and when I try to flash with the aocx file: aocl flash acl0 bin/vector_add.aocx aocl flash: Running flash from /tools/intelFPGA/18.0/hld/board/trasic/de5net/linux64/libexec Failed to open file: aocl flash: Flashing failed. Error reading aocx file. any idea that what step I am missing and what is causing this? why my aocx is not valid while the quartus project looks fine and compiled successfully? Is there any other way that I can program my fpga with the generated project?Implementing "Wait" or "Sleep" in HLS module
I want to write a HLS module(writing in C and using i++) that periodically(almost every second) copies a block of memory to another location. How can I implement the wait time? should I just implement a for loop without body? how can I be sure that optimizer doesn't get rid of it since it doesn't do anything?Re: creating aocx file from Quartus project
@HRZ I am not sure how HLS compiler solves my problem. I have a program written for Intel OpenCL SDK, I don't think HLS can compile it unless I write the program all over again and not use the OpenCL. As I said before, I need to use chip planner and partition planner. There should be an easier way than writing the whole program again and retargeting it for HLS.Re: creating aocx file from Quartus project
Then what is the point of creating a Quartus project if I can't use it? Why wouldn't I be able to change the aoc and continue the flow as before? Particularly right now I don't want to change the RTL but I want to use chip plan/design partition. Would that be possible?Error when running Quartus project generated by OpenCL
I compiled a kernel with OpenCL SDK for FPGA, it successfully finishes. But when I open the project that is automatically generated and try to run it I get this error after a while: Info (21057): Implemented 5 device resources after synthesis - the final resource count might be different Info (21058): Implemented 3 input pins Info (21059): Implemented 1 output pins Info (21061): Implemented 1 logic cells Info (281019): Starting Logic Optimization and Technology Mapping for Partition acl_kernel_partition Info (18062): Inserted logic cells for Maximum Fan-Out assignment Info (18058): Inserted 3 logic cells for Maximum Fan-Out assignment on "system:system_inst|system_kernel_system:kernel_system|conv_pipe_system:conv_pipe_system|coreConv_std_ic_partition_wrapper:coreConv_std_ic_inst|coreConv_top_wrapper_0:coreConv_inst_0|coreConv_function_wrapper:kernel|coreConv_function:thecoreConv_function|bb_coreConv_B4:thebb_coreConv_B4|bb_coreConv_B4_stall_region:thebb_coreConv_B4_stall_region|i_acl_push_i1_throttle_push_coreconv826:thei_acl_push_i1_throttle_push_coreconv|acl_push:thei_acl_push_i1_throttle_push_coreconv827|acl_token_fifo_counter:fifo|valid_counter[0]" Info (18058): Inserted 4 logic cells for Maximum Fan-Out assignment on "system:system_inst|system_kernel_system:kernel_system|conv_pipe_system:conv_pipe_system|maxPool_std_ic_partition_wrapper:maxPool_std_ic_inst|maxPool_top_wrapper_0:maxPool_inst_0|maxPool_function_wrapper:kernel|maxPool_function:themaxPool_function|bb_maxPool_B4:thebb_maxPool_B4|bb_maxPool_B4_stall_region:thebb_maxPool_B4_stall_region|i_acl_push_i1_throttle_push_maxpool957:thei_acl_push_i1_throttle_push_maxpool|acl_push:thei_acl_push_i1_throttle_push_maxpool958|acl_token_fifo_counter:fifo|valid_counter[0]" Info (18058): Inserted 3 logic cells for Maximum Fan-Out assignment on "system:system_inst|system_kernel_system:kernel_system|conv_pipe_system:conv_pipe_system|memRead_std_ic_partition_wrapper:memRead_std_ic_inst|memRead_top_wrapper_0:memRead_inst_0|memRead_function_wrapper:kernel|memRead_function:thememRead_function|bb_memRead_B10:thebb_memRead_B10|bb_memRead_B10_stall_region:thebb_memRead_B10_stall_region|i_acl_push_i1_throttle_push_memread558:thei_acl_push_i1_throttle_push_memread|acl_push:thei_acl_push_i1_throttle_push_memread559|acl_token_fifo_counter:fifo|valid_counter[0]" Info (17049): 4790 registers lost all their fanouts during netlist optimizations. Info (21057): Implemented 157517 device resources after synthesis - the final resource count might be different Info (21058): Implemented 1171 input pins Info (21059): Implemented 1296 output pins Info (21061): Implemented 129615 logic cells Info (21064): Implemented 25255 RAM segments Info (21062): Implemented 180 DSP elements Info (144001): Generated suppressed messages file D:/test/test/top.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1265 warnings Info: Peak virtual memory: 12689 megabytes Info: Processing ended: Fri Jul 31 00:30:53 2020 Info: Elapsed time: 00:38:12 Info: Total CPU time (on all processors): 00:44:12 Info: ******************************************************************* Info: Running Quartus Prime Partition Merge Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Processing started: Fri Jul 31 00:31:01 2020 Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off top -c top --merge=on Info: Using INI file D:/test/test/quartus.ini Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Error (35001): Missing required database file "D:/test/test/incremental_db/compiled_partitions/top.root_partition.map.cdb" for the partition "Top" Error: Quartus Prime Partition Merge was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 4785 megabytes Error: Processing ended: Fri Jul 31 00:31:14 2020 Error: Elapsed time: 00:00:13 Error: Total CPU time (on all processors): 00:00:13 Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 1266 warnings Any idea what is wrong?OpencCL compiler fails after installing license
I just bought a Quartus license and installed it. I am trying to use the Opencl compiler(I used to be able to use it with no problem on trial license). when I run the compiler I get this error: /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware$ aoc device/swap_mem.cl -o bin/swap_mem.aocx --board de5net_a7 --report -- profile Warning: Command has been deprecated. Please use -board=<value> instead of --board <value> Warning: Command has been deprecated. Please use -report instead of --report Warning: Command has been deprecated. Please use -profile instead of --profile aoc: Warning: no argument provided for the option -profile, will enable profiling for all kernels by default aoc: Selected target board de5net_a7 aoc: Running OpenCL parser.... /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/device/swap_mem.cl:14:34: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance __global float *A, ^ /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/device/swap_mem.cl:15:18: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance __global int* trigger, ^ 2 warnings generated. aoc: Optimizing and doing static analysis of code... !=========================================================================== ! The report below may be inaccurate. A more comprehensive ! resource usage report can be found at swap_mem/reports/report.html !=========================================================================== +--------------------------------------------------------------------+ ; Estimated Resource Usage Summary ; +----------------------------------------+---------------------------+ ; Resource + Usage ; +----------------------------------------+---------------------------+ ; Logic utilization ; 20% ; ; ALUTs ; 13% ; ; Dedicated logic registers ; 9% ; ; Memory blocks ; 23% ; ; DSP blocks ; 1% ; +----------------------------------------+---------------------------; Compiling for FPGA. This process may take a long time, please be patient. Error (138079): Current license file does not support partial reconfiguration. The Quartus Prime software automatically disabled partial reconfiguration support on all partitions. Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 0 warnings Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 0 warnings Error: Flow compile (for project /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/top) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. Error (23031): Evaluation of Tcl script /tools/intelFPGA/18.0/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 10 errors, 0 warnings Error: Compiler Error, not able to generate hardware Any idea what the problem is? this is the content of quartus_sh_compile.sh: Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Wed Jul 29 22:48:07 2020 Info: Command: quartus_sh --flow compile top -c top Info: Quartus(args): compile top -c top Info: Using INI file /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/quartus.ini Info: Project Name = /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/top Info: Revision Name = top Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Processing started: Wed Jul 29 22:48:34 2020 Info: Command: quartus_sh -t scripts/pre_flow.tcl compile top top Info: Quartus(args): compile top top Info: Using INI file /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/quartus.ini Info: Deleting incremental_db to ensure imported partition is only used Info: Checking for OpenCL SDK installation, environment should have INTELFPGAOCLSDKROOT defined Info: INTELFPGAOCLSDKROOT=/tools/intelFPGA/18.0/hld Info: Compiling CvP! Info (23030): Evaluation of Tcl script scripts/pre_flow.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Peak virtual memory: 750 megabytes Info: Processing ended: Wed Jul 29 22:48:35 2020 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Processing started: Wed Jul 29 22:48:38 2020 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top Info: Using INI file /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/quartus.ini Error (138079): Current license file does not support partial reconfiguration. The Quartus Prime software automatically disabled partial reconfiguration support on all partitions. Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 0 warnings Error: Peak virtual memory: 909 megabytes Error: Processing ended: Wed Jul 29 22:49:08 2020 Error: Elapsed time: 00:00:30 Error: Total CPU time (on all processors): 00:00:30 Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 0 warnings Error: Flow compile (for project /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/top) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. Error (23031): Evaluation of Tcl script /tools/intelFPGA/18.0/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 10 errors, 0 warnings Error: Peak virtual memory: 804 megabytes Error: Processing ended: Wed Jul 29 22:49:09 2020 Error: Elapsed time: 00:01:02 Error: Total CPU time (on all processors): 00:01:01 this is how my license setup looks like:Error compiling OpenCL kernel for FPGA after license install
I just bought a Quartus license and installed it. I am trying to use the Opencl compiler(I used to be able to use it with no problem on trial license). when I run the compiler I get this error: /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware$ aoc device/swap_mem.cl -o bin/swap_mem.aocx --board de5net_a7 --report -- profile Warning: Command has been deprecated. Please use -board=<value> instead of --board <value> Warning: Command has been deprecated. Please use -report instead of --report Warning: Command has been deprecated. Please use -profile instead of --profile aoc: Warning: no argument provided for the option -profile, will enable profiling for all kernels by default aoc: Selected target board de5net_a7 aoc: Running OpenCL parser.... /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/device/swap_mem.cl:14:34: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance __global float *A, ^ /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/device/swap_mem.cl:15:18: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance __global int* trigger, ^ 2 warnings generated. aoc: Optimizing and doing static analysis of code... !=========================================================================== ! The report below may be inaccurate. A more comprehensive ! resource usage report can be found at swap_mem/reports/report.html !=========================================================================== +--------------------------------------------------------------------+ ; Estimated Resource Usage Summary ; +----------------------------------------+---------------------------+ ; Resource + Usage ; +----------------------------------------+---------------------------+ ; Logic utilization ; 20% ; ; ALUTs ; 13% ; ; Dedicated logic registers ; 9% ; ; Memory blocks ; 23% ; ; DSP blocks ; 1% ; +----------------------------------------+---------------------------; Compiling for FPGA. This process may take a long time, please be patient. Error (138079): Current license file does not support partial reconfiguration. The Quartus Prime software automatically disabled partial reconfiguration support on all partitions. Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 0 warnings Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 0 warnings Error: Flow compile (for project /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/top) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. Error (23031): Evaluation of Tcl script /tools/intelFPGA/18.0/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 10 errors, 0 warnings Error: Compiler Error, not able to generate hardware Any idea what the problem is? this the content of quartus_sh_compile.sh: Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Wed Jul 29 22:48:07 2020 Info: Command: quartus_sh --flow compile top -c top Info: Quartus(args): compile top -c top Info: Using INI file /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/quartus.ini Info: Project Name = /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/top Info: Revision Name = top Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Processing started: Wed Jul 29 22:48:34 2020 Info: Command: quartus_sh -t scripts/pre_flow.tcl compile top top Info: Quartus(args): compile top top Info: Using INI file /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/quartus.ini Info: Deleting incremental_db to ensure imported partition is only used Info: Checking for OpenCL SDK installation, environment should have INTELFPGAOCLSDKROOT defined Info: INTELFPGAOCLSDKROOT=/tools/intelFPGA/18.0/hld Info: Compiling CvP! Info (23030): Evaluation of Tcl script scripts/pre_flow.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Peak virtual memory: 750 megabytes Info: Processing ended: Wed Jul 29 22:48:35 2020 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Info: Processing started: Wed Jul 29 22:48:38 2020 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top Info: Using INI file /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/quartus.ini Error (138079): Current license file does not support partial reconfiguration. The Quartus Prime software automatically disabled partial reconfiguration support on all partitions. Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 0 warnings Error: Peak virtual memory: 909 megabytes Error: Processing ended: Wed Jul 29 22:49:08 2020 Error: Elapsed time: 00:00:30 Error: Total CPU time (on all processors): 00:00:30 Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 0 warnings Error: Flow compile (for project /tools/intelFPGA/18.0/hld/board/trasic/de5net/tests/swap_mem_malware/bin/swap_mem/top) was not successful Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last. Error (23031): Evaluation of Tcl script /tools/intelFPGA/18.0/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 10 errors, 0 warnings Error: Peak virtual memory: 804 megabytes Error: Processing ended: Wed Jul 29 22:49:09 2020 Error: Elapsed time: 00:01:02 Error: Total CPU time (on all processors): 00:01:01 this is how my license setup looks like:
