EricMunYew_C_IntelFrequent ContributorJoined 5 years ago537 Posts3 LikesLikes received16 SolutionsView All Badges
ContributionsMost RecentMost LikesSolutionsRe: How can arria 10 GX FPGA be used in unbutu20.04 I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Re: Platform Designer error, Cyclone-V SOC, generate_hps_sdram.tcl I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Re: Quartus 18.1 Lite Platform Designer DDR3 Controller can't build when WSL is enabled I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Re: I2C master ip: How/where are the bidirectional open drain line buffers? I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Re: OPAE-Intel FPGA Drivers I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Re: a very simple question about Nios2 eclipse project build I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Re: Platform Designer error, Cyclone-V SOC, generate_hps_sdram.tcl You can try below. https://www.intel.com/content/www/us/en/support/programmable/articles/000074066.html Re: Platform Designer Error, please help I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Re: Using OpenCL vector type with channels: Assert failure in MemoryAccessAnalysis.cpp(219) I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Re: DE1-SOC I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.