SteveMellor
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Re: Agilex™ 5 FPGA E-Series 065B Modular Dev Kit PCIe design does not build after tool version upgrade
Upgrading the IP regenerates all of the QSYS and RTL files for the IP. It seems the example design was created by editing of RTL files generated by the tools. The edits are overwritten when the IP is regenerated. The edits need to be restored to the top level of the design: examples\pcie_ed\pcie_ed_24p1\pcie_ed\synth\pcie_ed.v The edits can be restored by copying the original file from the example over the regenerated file. One module will have changed name when regenerated though and this name needs to be corrected in the pcie_ed.v file. Find the module pcie_ed_altera_mm_interconnect_1920_4uhoqna in the pcie_ed.v file. This module name needs to match the new name. The correct name to use can be found in the RTL file name in this directory: examples\pcie_ed\pcie_ed\pcie_ed\altera_mm_interconnect_1920\synth The new file name changes the last few characters e.g. pcie_ed_altera_mm_interconnect_1920_k23lfcq797Views0likes0CommentsAgilex™ 5 FPGA E-Series 065B Modular Dev Kit PCIe design does not build after tool version upgrade
The dev kit design examples are available here: https://www.intel.com/content/www/us/en/content-details/826413/agilex-5-fpga-e-series-065b-modular-development-kit-v24-1-or-higher.html The current design examples download as this zip file. agilex5e_modular_es_a5ed065bb32ae6sr0_qii24.1b115_v1.0.zip They are designed for the 2024.1 tool flow. There are two mistakes in the PCIe design example. The QSF file examples\pcie_ed\pcie_ed\pcie_ed.qsf is missing the following assignment set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ The SDC file examples\pcie_ed\pcie_ed\sm_pciess_ed.sdc.terp on line 14 ends with a '-group' option with no target specified. This final '-group' text needs to be removed Building the design in a later tool version without upgrading the IP works. Upgrading the IP results in errors. Error(22412): The design requires at least 914 elements of type IO_PAD but the device has only 721. Info(22413): IP pcie_ed pcie_ed requires elements of this type. Info(22414): Node: I/O pad pio0_tx_pio_tdata[0]. Info(22414): Node: I/O pad pio0_tx_pio_tdata[1]. Info(22414): Node: I/O pad pio0_tx_pio_tdata[2]. Info(22414): Node: I/O pad pio0_tx_pio_tdata[3]. Info(22414): Node: I/O pad pio0_tx_pio_tdata[4]. Info(22414): Node: I/O pad pio0_tx_pio_tdata[5]. Info(22414): Node: I/O pad pio0_tx_pio_tdata[6]. Info(22414): Node: I/O pad pio0_tx_pio_tdata[7]. Info(22414): Node: I/O pad pio0_tx_pio_tdata[8]. Info(22414): Node: I/O pad pio0_tx_pio_tdata[9]. Info(22411): 904 others not shown. Set DRC_DETAIL_MESSAGE_LIMIT to change the number of nodes shown here.Solved808Views0likes2CommentsRe: Select the PLL reference clock used for timing analysis
I have been using derive_pll_clocks but it uses the slower of the two input clocks for timing analysis. The clock tree analysis shows this. Reporting the timing of any path clocked by the output of the PLL also shows that it is using the slower clock period. The device is an Arria 10.1.3KViews0likes0CommentsSelect the PLL reference clock used for timing analysis
When a PLL has multiple reference clock inputs how can you define the one to use for timing analysis? The tool is selecting the first reference clock (pll_refclk0) for timing analysis but this is the slower of two reference clocks. The clock inputs cannot be swapped in the RTL as the slower clock is running when the PLL and transceivers are configured.Solved1.4KViews0likes7Comments