ContributionsMost RecentMost LikesSolutionsWhat is the point of eSRAM and how do you use it? I'm developing for an Agilex 7 board which is equipped with about 36 Mbit of eSRAM and 146 Mbit of M20K. Since the M20K memory is both larger and has lower access latency than the eSRAM, what is the point of using the latter? Also, is it possible to get Quartus to infer eSRAM when using Intel OpenCL or DPC++? Re: Why does aoc set ii to 6 when I use high clock frequencies? Hi @BoonBengT_Altera , I'm using the Intel OpenCL Compiler. So the reports I'm referring to are those produced by that compiler. I'm trying to get it to make designs with 700 MHz. Re: Why does aoc set ii to 6 when I use high clock frequencies? The hardware is Agilex 7 F-Series. The software is aoc Version 21.2.0 Build 67.4 Pro Edition. No error messages or anything like that. I know 1000 MHz is much for the fpga but I'm seeing the same issue even with 700 MHz which the fpga should be able to handle. Why does aoc set ii to 6 when I use high clock frequencies? I have a simple toy that I want to run at 1000 MHz kernel that doesn't do much: __attribute__((uses_global_work_offset(0))) __attribute__((max_global_work_dim(0))) __kernel void netsim( __global const volatile float * restrict gl_vm ) { float vm[50000]; #pragma ii 1 #pragma ivdep #pragma speculated_iterations 64 for (int i = 0; i < 50000; i++) { vm[i] = gl_vm[i]; } } According to the report (see screenshot), II=6 and latency=927. Why can't the compiler lower the latency and set II to 1 here?