hazeltet845
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Re: Rule C101 and PLL output clock
I added the reset to the sensitivity list and am still getting the critical warning "Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) related to this rule". Do you know how to fix this critical warning? I think it is possibly the reason I am not meeting timing requirements.1.5KViews0likes0CommentsRule C101 and PLL output clock
I am using Quartus II 10.1 and keep receiving the critical warning "Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) related to this rule". It says the node related to this rule is the 200 MHz clock output of my PLL that I created using the ALTPLL Megafunction. I made sure in the .sdc file that I have "derive_pll_clocks" so that the fitter knows that this is a clock. It is only giving me this error when I try to use "rising_edge(clk)" or "falling_edge(clk)" with the PLL generated clock like in the example below. cnt : process(clk) is begin if(reset = '1') then r_CNT <= (others => '0'); elsif (rising_edge(clk)) then temp(0) <= input and enable; temp(1) <= temp(0); temp(2) <= not temp(1) and temp(0); if (temp(2) = '1') then r_CNT <= r_CNT + 1; else r_CNT <= r_CNT; end if; end if; end process cnt;Solved1.5KViews0likes4Commentsv1495 Quartus II device library
Hello, I am trying to use the CAEN v1495 board in Quartus II 13.1 Web edition. I know that this board is not supported in version 13.1 so I need an earlier version of Quartus II. The Intel website does not allow downloads of this software for earlier versions than 13.1. Is there anywhere I can find ways to download earlier versions, like 10.1? Or is there any way to gain access to download earlier versions from Intel. Thank you1.1KViews0likes4Comments