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hazeltet845's avatar
hazeltet845
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4 years ago
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Rule C101 and PLL output clock

I am using Quartus II 10.1 and keep receiving the critical warning "Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) ...
hazeltet845's avatar
hazeltet845
Icon for New Contributor rankNew Contributor
4 years ago

I added the reset to the sensitivity list and am still getting the critical warning "Critical Warning: (Critical) Rule C101: Gated clock should be implemented according to the Altera standard scheme. Found 1 node(s) related to this rule". Do you know how to fix this critical warning? I think it is possibly the reason I am not meeting timing requirements.