ContributionsMost RecentMost LikesSolutionsRe: Uniphy Platform Designer Error: "Cannot find sequencer/sequencer.elf" Sounds good that engineering will looks into this. Please note the probably related issue in https://community.intel.com/t5/Programmable-Devices/Quartus-18-1-Lite-Platform-Designer-DDR3-Controller-can-t-build/m-p/1339839#M82242 Re: Quartus 18.1 Lite Platform Designer DDR3 Controller can't build when WSL is enabled Any comments on this ? Please note the probably related issue in https://community.intel.com/t5/Intel-Quartus-Prime-Software/Uniphy-Platform-Designer-Error-quot-Cannot-find-sequencer/m-p/1341293/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufEtXUU1CMkdZN1dKVUVZfDEzNDEyOTN8U1VCU0NSSVBUSU9OU3xoSw#M71624 Re: How effective is the video Frame Buffer core when storing in memory? Hi Zul, The frequencies are pretty moderate with DDR3 at 400 MHz and video pipe at 112.5 MHz in a Cyclone V device, with pixel rate of 2 per cycle. As I noted, the question was answered based on the reference I made above, with information about how the VFB stores data on the Avalon-MM IF. That will be linear, but for best efficiency then Bank-Row-Column mode must be used in the DDR3, with frame spacing that ensure different frames goes in different banks, to benefit from open row on both write and read side of the VFB. Best regards MoZdk Quartus 18.1 Lite Platform Designer DDR3 Controller can't build when WSL is enabled For a project with a DDR3 SDRAM Controller, I am using Quartus 18.1 Lite with Platform Designer on a Windows 10 PC. After installing WSL (Windows Subsystem for Linux), an error occurs when I try to generate code in Platform Designer., even trough Quartus 18.1 should not depend on WSL. The immediate error is "Cannot find sequencer/sequencer.elf", where it appears that a Makefile fails to generate the file sequencer.elf. When looking into the Quartus 18.1 scripts, is appears that the bash script: "c:/intelFPGA_lite/18.1/nios2eds/sdk2/bin/nios2-bsp" is not run from a generated temporary Makefile, which has the line: C:/intelfpga_lite/18.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE The Makefile is run through the script: c:/intelFPGA_lite/18.1/nios2eds/nios2_command_shell.sh with the line: exec $@ where the argument $@ is: make all 2>> stderr.txt So it appears, that somehow enable of WSL causes execution of the bash script "c:/intelFPGA_lite/18.1/nios2eds/sdk2/bin/nios2-bsp" to fail when it is called from the temporary Makefile. The error and some script arguments are shown in the picture below. Error in PD when building DDR3 Ctrl. code after installation of WSL If I disable WSL in Windows 10, then generation of code in Platform Designer works again. Since WSL is mandatory for e.g. Quartus 21.3 Pro, which I also have to use, it effectively requires me to enable and disable WSL and then reboot my PC each time I go between Quartus 18.1 Lite and Quartus 21.3 Pro. Note that another, and *maybe* related, problem with DDR3 controller and WSL has been reported in e.g. https://community.intel.com/t5/Intel-Quartus-Prime-Software/Uniphy-Platform-Designer-Error-quot-Cannot-find-sequencer/m-p/1329216#M71416 Re: How effective is the video Frame Buffer core when storing in memory? . Re: How effective is the video Frame Buffer core when storing in memory? The information is in document ""Video and Image Processing Suite User Guide (UG-VIPSUITE | 2021.02.12)" section "16.7.3. Memory Map for Frame Reader or Writer Configurations" paragraph "The frame data is tightly packed into memory and aligned on frame (or field) boundaries to minimize storage usage and maximize memory bandwidth usage." So the data is tightly packed in memory. How effective is the video Frame Buffer core when storing in memory? The Video and Image Processing (VIP) Suite IP has a Video Frame Buffer (VFB) core, named Frame Buffer II IP Core, that can take streaming images on the Avalon-ST IF and save it into memory using Avalon-MM IF, for using a DDR3 memory controller. In my application, the VFB Frame Buffer II IP Core has these interfaces: - Streaming video: Avalon-ST IF width 48 bits (for 2 pixels in parallel of each 24 bits) - Memory interface: Avalon-MM IF width 64 bit Since the memory bandwidth is critical, I want to determine the expected amount of overhead, but I am unable to find any information about this in the "Video and Image Processing Suite User Guide (UG-VIPSUITE | 2021.02.12)". So, how effectively does the VFB Frame Buffer II IP Core pack the 48-bit Avalon-ST IF data into the memory using the 64-bit Avalon-MM IF ? For example, is the 48 bit Avalon-ST data packed back-to-back in memory, or is the 48-bit Avalon-ST data aligned to the 64-bit Avalon-MM data size, thereby introducing an overhead of 33 %. SolvedRe: Uniphy Platform Designer Error: "Cannot find sequencer/sequencer.elf" Installation of WSL (Windows Subsystem for Linux) breaks the Quartus lite 18.1 Platform Designer so it is not possible to generate code with the DDR3 controller, even through WSL is not expected to be used for Quartus 18.1. The error messages are similar to those given in Quartus 21.1 shown above. When I disable WSL and restarts Windows, then the Quartus lite 18.1 Platform Designer can again generate code with the DDR3 controller. Re: Uniphy Platform Designer Error: "Cannot find sequencer/sequencer.elf" Thanks for posting this thorough problem report. I am also running Quartus Prime Std 21.1.0.842, tries to generate a design with a DDR3 controller, and thereby get the exact same error. I have also tried the suggestions given in this topic, which unfortunately have not fixed the problem. A solution i greatly appreciated, since it blocks use of Quartus Prime Std 21.1 for the design. How to ignore simulation only ports when mapping to FPGA pins? A design has a number of simulation ports that should not be tied to FPGA pins. A VHDL example is shown in the source below, where the sim_only_* ports are for simulation only, thus should not be mapped to FPGA pins. entity mdl is port( -- FPGA pins clk_i : in std_logic; rst_i : in std_logic; a_i : in std_logic; z_o : out std_logic; -- Simulation pins only sim_only_in : in std_logic := '0'; sim_only_out : out std_logic); end entity; The sim_only_* pins can be safely left unused by Quartus, since the inputs have default value. When running Quartus, the mapper tries to map the sim_only_* ports to unused FPGA pins, which is not desired. How can I specify that Quartus should just ignore the sim_only_* ports on the VHDL design? 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