altera33
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Transceiver scripting API can't open service
Hello, To the customer service, important note : "pls read this message and try to understand the problem." Wiki contains a standard example design "cv_GX_1ch_40b_3125mbps" that can be used to test the Transceiver Toolkit. The Toolkit GUI works as awaited: can open the link and make the tests (see blue marked results): So far so good .... An example contains also a TCL-script (link_test.tcl) for the scripting API based testing. But this script fails to open the data_pattern_generator service (see red market error message). The open_service doesn't report any errors but any access to the settings of the data_pattern_generator FAILS. % open_service data_pattern_generator "/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB-1#TDSUB2/(link)/JTAG/alt_sld_fab_sldfabric.node_0/phy_0/master_0.master/data_pattern_generator_0.csr_slave/driver" % data_pattern_generator_is_generating "/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB-1#TDSUB2/(link)/JTAG/alt_sld_fab_sldfabric.node_0/phy_0/master_0.master/data_pattern_generator_0.csr_slave/driver" error: data_pattern_generator_is_generating: /devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB-1#TDSUB2/(link)/JTAG/alt_sld_fab_sldfabric.node_0/phy_0/master_0.master/data_pattern_generator_0.csr_slave/driver is not an open data_pattern_generator service while executing "data_pattern_generator_is_generating "/devices/5CSEBA6(.|ES)|5CSEMA6|..@1#USB-1#TDSUB2/(link)/JTAG/alt_sld_fab_sldfabric.node_0/phy_0/master_0.master..." RegardsRe: Is it possible to get a good documentation?
Hi, i have a lot of customers switched from Altera to your next competitor, but the reason was not a bad hardware - FPGAs are good! - but a horrible support and documentation. My "question" is more a feedback to your company about the quality of your documentation, but you seems to be an automatic bot, that is not able to understand it. Such things like links to altera.com in your online Wiki; or different names between the IP catalog and the documentation; or missleading software documentation costs us - developers - time and makes stress. AGAIN: it is an open feedback. You don't need to explain me "how to open the PDF doc"- pls just improve your support, online wiki and docs. RegardsIs it possible to get a good documentation?
Hi, every new FPGA project with Altera/Intel FPGA was/is an adventure. First off all it is not really possible to plan an effort for new solution, because the documentation mostly never match the Quartus IP or functions. Very simple example with an Avalon FIFO: Step 1: IP in Quartus is called "Avalon FIFO Memory Intel FPGA IP". Now try to find this string in altera online documentation - wasted time. IP itself contain a link to ... 😂 "On-Chip FIFO Memory Core". Is it a same - nobody knows. Step 2: Now connect this IP with your control signals. Is it easy - of couse, can you do it after first attempt? Never! There is a "very unimportant signal" called "reset_in". If you are doing this job for a long time, than you know that this signal should have an active high logic. Otherwise is would be called "reset_in_n". Also documentation says nothing about the active level (it is not necessary - develper will play around and find a right one). ... an hour later (big design) you will mention, that your FIFO makes nothing, and "Oh Wonder!" the Signal Tap calls the reset signal "xyz_reset_reset_n". 😡 Step 3: Let use a software interface to control this IP by NIOS as it is described in the online docu. Next adventure 😠 : the write command altera_avalon_fifo_write_fifo() would like to get two addresses: WRITE and CONTROL. But the control port is optional! After some reverse engineering of the source code, you wiil find out, that the software interface it not for the CONTROLLING of the FIFO, but only to read/update status and to contol the interrupt handling. The CONTROL register is called ALTERA_AVALON_FIFO_OTHER_INFO_REG. Can you read it clearly smwh in the documentation? ... 😋 sorry it was a rhetoric question. Proposal: If you want to start the transmission, pls use the OLD, GOOD register access. Such situation i had mostly with ALL IPs from Altera. My rule of trumb for Altera FPGA projects is: estimate the "normal" effort and multiply by two! Because the crowling of the correct and not missleading information becomes a part of your job (not forget the reverse engineering) Now question to Intel/Altera support: What is a Known Good Practice proposed by you to get the correct and not missleading information about IPs! Now question to other FPGA developers: What is your experience with Altera/Intel Documentation?Re: How to use NAND in HPS baremetal program?
Hi, we have our own board and as i WROTE above the HW interface is working. The Linux driver works properly and we can read/write this NAND Flash. Therefore i have a feeling, that you are an automatic answering bot, because all your proposals have nothing to do with my questions. Is it a quality level of Intel support meanwhile? My only question was : "is there any c-code example for HPS HWLib NAND API?" Regards,How to use NAND in HPS baremetal program?
is there any c-code examples for HPS HWLib NAND API? My simple code is reading 0xFF whatever i wrote. I'm using MT29F8G08ABACAH4-IT. The linux driver is able to read/write this FLASH. ALT_PRINTF("NAND: Initializing NAND.\n"); status = alt_nand_init(ALT_NAND_BOOTSTRAP_INHIBIT_B0P0_LOAD_DISABLE, ALT_NAND_BOOTSTRAP_512B_DEVICE_DISABLE, init_nand, (void *)¶m); if (status != ALT_E_SUCCESS) ALT_PRINTF("NAND: Error initializing NAND.\n"); //alt_nand_ecc_enable(ALT_NAND_ECC_8_BIT_CORRECTION); alt_nand_ecc_disable(); for(int k=0;k<NAND_PAGE_SZ;k++) nand_buf[k]=k; status = alt_nand_write_page(0, 1, (uint32_t *)nand_buf); if (status != ALT_E_SUCCESS) ALT_PRINTF("NAND: Error writing NAND.\n"); memset(nand_buf,0,NAND_PAGE_SZ); status = alt_nand_read_page(0, 1, (uint32_t *)nand_buf); if (status != ALT_E_SUCCESS) ALT_PRINTF("NAND: Error reading NAND.\n"); else for(int k=0;k<NAND_PAGE_SZ;k++) if(nand_buf[k]!=k) { ALT_PRINTF("NAND:R/W Error @%d.\n",k); break; }On-chip RAM unavailable over JTAG
There is a VERY SIMPLE example how to create and start a HPS based "Hello World" app on Cyclone V SOC : https://www.intel.com/content/www/us/en/programmable/documentation/lro1424280108409.html Debugging is connected over USB-Blaster. Unfortenutely the debug step fails for both GCC abd DS-5 based apps. The app cannot be loaded into OCRAM (on LARK board and custom HW): loadfile "C:\FPGA\ws_arm\at_tst\Debug\at_tst.axf" Target Message: Memory access caused precise abort. Debug Precise Abort Registers : DFSR = 0x00000817, DFAR = 0x00100FE0 ERROR(CMD16-TAD274-NAL18): ! Failed to load "at_tst.axf" ! Failed to write 17.504 bytes to address S:0x00100000 while writing block of 4.096 bytes to address S:0x00100000 ! Bus error on memory operation. set debug-from main start WARNING(CMD399-COR168): ! Failed to start the target ! No function named "main" could be found WARNING(CMD407): Trying the entry point instead ERROR(CMD426): Cannot find symbol to start or entrypoint, the file or load commands may be used to set the entrypoint wait Debugger can access only in the range 0xFFFF0000-0xFFFF1FFF beginning with 0xFFFF2000 the OCRAM becomes unaccessible. Just a simple test: memory set_typed S:0xFFFF2000 (unsigned int) (0) Target Message: Memory access caused precise abort. Debug Precise Abort Registers : DFSR = 0x00000817, DFAR = 0xFFFF2000 ERROR(TAD11-NAL18): ! Failed to write 4 bytes to address S:0xFFFF2000 ! Bus error on memory operation Memory view: The problem seems to be not new, but the solution ...
