Hazlina_R_Intel
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Re: Sorting algorithm
Hi, Thanks for your question. Have you checked out the internet resources through any web search engine for the potential example codes that you can use to build your program? You may use the key word of "sorting algorithm using verilog" and you may find some example codes that you may use. -Hazlina1.3KViews0likes0CommentsRe: The Type of Support Offered By Intel
Hi, Thanks for your question and we appreciate your business with us. I think you are referring to another post that you had posted here: https://community.intel.com/t5/forums/forumtopicpage/board-id/quartus-prime-software/message-id/69533#M69533 FYI, an engineer has been assigned to the case and I have asked him to expedite the response to your question. The team had a long weekend break, hence the delay in the response. All the questions that come into this community portal will be assigned to an engineer who will work on addressing the questions. We have a team of 24 engineers who are working in the team currently to do this. If you do not get a response, please simply reply back to the post that you made and ask for a response OR you can choose to do what you just did: raising another post to get the escalated support. A manager for the team will be able to respond to you accordingly. Thanks for your cooperation. -Hazlina979Views0likes0CommentsRe: DMA Controller with external DREQ/DACK mechanism on CPLD or FPGA
This is the latest link for AN492: https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/compactflash-interface-an-492/?wapkw=an492 We have other design examples in our Design Store here: https://fpgacloud.intel.com/devstore/ For DMA controller IP you may refer to the brief here: https://www.intel.com/content/www/us/en/secure/design/internal/content-details.html?DocID=618538 On your question on the feasibility to use Nios II embedded processor IP core in addition to the IDE/ATA controller core and the DMA controller core in one single device without a microcontroller, let me get an engineer to assess this for you. -Hazlina3.2KViews0likes2CommentsRe: DMA Controller with external DREQ/DACK mechanism on CPLD or FPGA
Hi, Thanks for your question. You may check out this white paper: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/wp/wp-01041-six-ways-to-replace-microcontroller-with-cpld.pdf It made references to some very old CPLD products that we have but the basic principles still apply. For the list of the newer CPLDs, you may visit this page: https://www.intel.com/content/www/us/en/products/details/fpga/max.html -Hazlina3.2KViews0likes1CommentRe: Getting OpenVINO Inference Time per Layer
Hi, We will be able to answer questions related to the FPGA, for the inference time. For processor/CPU related, please raise a new question under OpenVino forums here: https://community.intel.com/t5/Intel-Distribution-of-OpenVINO/bd-p/distribution-openvino-toolkit For your question on the inference time, which deep learning model are you interested with? Can you be more specific on your use cases? I will get an engineer to look into this. -Hazlina1.4KViews0likes1Comment