malayali
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Re: LRDIMM DDR4 Failure to write was encountered on Arria10 FPGA. Please share your ideas.
Hi AdzimZM, We have tested DDR4 128GB write and read from the FPGA directly and it is working. Yet to test the same through the DMA, We are enabling the DMA from the firmware and Writing 128GB from the FPGA and Reading it through Read DMA Then cross verify. Once after this testing then I will post the reply.1.4KViews0likes1CommentRe: LRDIMM DDR4 Failure to write was encountered on Arria10 FPGA. Please share your ideas.
Hi, Our FPGA team did an exercise, Reading and writing to DDR4 from FPGA for 8GB without DMA access, this part is working. So I suggested doing 64GB and 128GB data read and write. The 64GB and 128GB is read and write is working as expected. Could you pl let me know what all screen shot required?1.5KViews0likes0CommentsRe: LRDIMM DDR4 Failure to write was encountered on Arria10 FPGA. Please share your ideas.
Hi ! Actually, we have done DDR4 calibration on every board and that is working perfectly but with all the functionality integrated JIC has the issue, We are able to read the data from DDR4 through PCIe and we compared the same from the FPGA and Jetson DVK. Its matching, So read activity is performing but the write has the issue.1.5KViews0likes0CommentsLRDIMM DDR4 Failure to write was encountered on Arria10 FPGA. Please share your ideas.
Hi, I work as a hardware designer. In my design, I used an Arria10 FPGA and an LRDIMM DDR4 module. I connected an FPGA to a processor using PCIe x8. The procedure is as follows: the FPGA receives certain Display port data from various devices, and the FPGA must write to the DDR4 LRDIMM Module (256Gb). This Processor will read the signal through PCIe x8 after the write. The processor will then write data to DDR4 through DMA in the FPGA. The problem is that the processor can read DDR4 data from the FPGA but not write it. Is there anything I need to change in the Quartus prime tool? What all settings must be checked. I have several boards, and only one of them is operational. The second is that it works sometimes and does not function other times. The remaining sets are completely ruined. From the hardware perspective there are no problems in the power or any issue. Pl suggest. DDR4 IBIS Models Arria10 DDR4 About Arria10 configuration Arria 10 DDR4 issues1.6KViews0likes10CommentsRe: Quartus Prime Software system debugging tool support
Hi Goel, Thank you for providing this useful information. I noticed that when I first ran in High gain mode, no BER showed. However, if I switch from High gain to High datarate mode, there is no BER in Lower datarate (RBR), but if I switch back to High gain mode, the BER appears. While I was performing the test, I didn't shut the toolkit. Does it because of a tool problem? Sometimes tools crash as well.1.2KViews0likes0CommentsQuartus Prime Software system debugging tool support
Hi , I'm using the System debugging toolkit from the Quartus prime software and changing Rx and Tx parameters for the DP 1.4 to test loop back, using Arria10 based on our own designed board. Pl clarify the following queries. 1) Once I open the system console then I'm selecting the FPGA configuration file. then the collection is added sometime automatically consol gets closed(Crashed). Any reason? 2) Once the collection of 6 Rx and Tx pairs is added then I need to set VOD, Pre-emphasis 1st post-tap, Pre-emphasis 1st pre-tap for the Tx path and for Rx path, CTLE DC_gain, CTLE AC_gain, VGA DC gain to be set, with High gain mode equalizer engine. Then I'm selecting everything and start the loop back and check the BER. If I need to change the equalizer engine to High datarate after High gain mode then once after setting, Do I need to close and reopen the tool? 3) Why I'm not able to change CTLE_DC gain, CTLE_AC Gain and VGA DC Gain in High datarate mode for Rx path? 4) If I run the same settings in high gain mode multiple times, E.g. close the tool after the first run then again open the tool and set the same settings then If I run, I m getting BER. But the same procedure If I do it again (Close tool then reopen, Do same settings), there is no BER. Is there any reason? Could you pl let me know, to perform these test is there any specific steps to follow? Let me know your thoughts.1.3KViews0likes5CommentsRe: Arria10 FPGA SERDES common mode voltage
hello Team, I am using Arria 10 FPGA my design. My application is USB (Host and device) and DP (Source and sink). I am using the Transceiver bank for the USB and DP interface and I have a few queries in it. 1. When FPGA is in DP Sink or USB Device [Receiver] mode will there be any common-mode voltage or bias voltage to the Multiplexer IC [TMUXHS4412] from the FPGA. I'm muxing the USB and DP Signals via these mux to the USB - C Connector. Please find the attached block diagram. 2. What is the common-mode voltage of the transceiver bank in Source and Sink USB or DP IP?1.4KViews0likes0Comments- 1.4KViews0likes0Comments