Gopikrishnan
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Re: Error with VCS simulator
Steps followed: I took the vcsmx_setup.sh script followed the steps mentioned in the script to create new top level script with my RTL files as well and tried compilation. But this is the error I'm getting Include files are not found for hls generated codes. There are some syntax related error as well. This is my top level script #QSYS_SIMDIR is used in the Quartus-generated IP simulation script to # # construct paths to the files required to simulate the IP in your Quartus # # project. By default, the IP script assumes that you are launching the # # simulator from the IP script location. If launching from another # # location, set QSYS_SIMDIR to the output directory you specified when you # # generated the IP script, relative to the directory from which you launch # # the simulator. In this case, you must also copy the generated library # # setup "synopsys_sim.setup" into the location from which you launch the # # simulator, or incorporate into any existing library setup. # # # # Run Quartus-generated IP simulation script once to compile Quartus EDA # # simulation libraries and Quartus-generated IP simulation files, and copy # # any ROM/RAM initialization files to the simulation directory. # # # # - If necessary, specify any compilation options: # # USER_DEFINED_COMPILE_OPTIONS # # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler # # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler # # source /home/graveen1/hls_20.3/feat_trans_ctrl_20.3/sim/synopsys/vcsmx/vcsmx_setup.sh \ SKIP_ELAB=1 \ SKIP_SIM=1 \ # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \ # USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \ USER_DEFINED_VERILOG_COMPILE_OPTIONS= -assert svaext QSYS_SIMDIR=/home/graveen1/hls_20.3/feat_trans_ctrl_20.3/sim/ #USER_DEFINED_ELAB_OPTIONS="'-assert svaext'" # # # # Compile all design files and testbench files, including the top level. # # (These are all the files required for simulation other than the files # # compiled by the IP script) # # vlogan -timescale=1ns/1ns -f ./verilogfiles.txt -top feat_tran_tb -sverilog +incdir+"/home/graveen1/hls_20.3/feat_trans_ctrl_20.3/sim/synopsys/vcsmx/libraries" +incdir+"/home/graveen1/hls_20.3/feat_trans_ctrl_20.3/" | tee comp_rtl.log # # # # TOP_LEVEL_NAME is used in this script to set the top-level simulation or # # testbench module/entity name. # # # # Run the IP script again to elaborate and simulate the top level: # # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS. # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run # # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="". # # source /home/graveen1/hls_20.3/feat_trans_ctrl_20.3/sim/synopsys/vcsmx/vcsmx_setup.sh \ SKIP_FILE_COPY=1 \ SKIP_DEV_COM=1 \ SKIP_COM=1 \ TOP_LEVEL_NAME="'-top feat_tran_tb'" \ QSYS_SIMDIR=/home/graveen1/hls_20.3/feat_trans_ctrl_20.3/sim/ \ USER_DEFINED_ELAB_OPTIONS="'-sverilog'" \ USER_DEFINED_SIM_OPTIONS="" # # ~Memory error when trying to simulate matrix multiplication using HLS math lib
component void test(ihc::stream_in<int> &matrixData,ihc::stream_in<int> &matrixData2,ihc::stream_out<int> &matrixout,bool ld, int dim_in,int dim_out){ ////////////input and output matrix definition///////// hls_memory hls_singlepump hls_max_replicates(1) hls_bankwidth(sizeof(int)) int feat_matrix[N_FEAT][N_COLS_1]; hls_memory hls_singlepump hls_max_replicates(1) hls_bankwidth(sizeof(int)) static int weight_matrix[N_COLS_1][N_COLS_2]; int out_feat[N_FEAT][N_COLS_2]; /////////////////////////////////////////// //////////populate the feature and weight matrix////////// for (int i=0; i <N_FEAT ; i++){ for(int j=0 ; j<N_COLS_1 ; j++){ feat_matrix[i][j] = matrixData.read(); } } if (ld){ for (int i=0; i <N_COLS_1 ; i++){ for(int j=0 ; j<N_COLS_2 ; j++){ bool success = false; weight_matrix[i][j] = matrixData2.tryRead(success); } } } /////////////////////////////////////////////////////// ////////MAT MUL AND WRITE BACK TO STREAM///////////// matrix_multiply<int,N_FEAT,N_COLS_1,N_COLS_2,N_DSP,N_DSP>(feat_matrix,weight_matrix,out_feat); for (int i=0; i <N_FEAT ; i++){ for(int j=0 ; j<dim_out ; j++){ matrixout.write(out_feat[i][j]); } } //////////////////////////////////////////////////// //////////////////////////////////////////////////// } When I'm trying to simulate this matrix multiplication for large dimensions it's giving me mem error Fatal vsim4 memory allocation failure. I figured out it's the loop unrolling that it's causing the issue. When I try to simulate the code using simple for loops with no unrolling it works fine. Is there any work around this or is there a better way of coding thisError with VCS simulator
I've generated a design using HLS and is trying to simulate the design using vcs script generated by HLS in the verification directory. But it is throwing syntax errors while compiling the code. The same codes were compiled properly using modelsim Any tips to work around this issue will be really helpfulHLS component invocation
Hello, I've a design with 2 components. The output from the first component is fed to the second component. While the second component is working I want the first component to work on a new set of inputs. Is this possible to achieve this. My understanding is the main function executes sequentially so only one component can be active at a time according to the sequential flow of the main. Is it possible to run two components parallelly from the main function?HLS component invocation question
1. Can I call another component from within a component similar to instantiating another rtl module within a module? 2. In the above code snippet I am calling the test twice from the main module. The second time I want to accumulate the sum with the sum from the previous call. But it is not happening. The sum register value is automatically set to 0 every time when component test is called. It's not holding the value from the previous call. Is there any way to achieve this?HBM2 example design memory initialization
Hello, I've generated the HBM2 example design for stratix10MX and simulated it. Now I want to initialize the HBM memory model provided with some values. Is it possible to do readmemh or something and initialize the hbm memory model or do I have to write it using the transaction generator to the HBM.?
