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Megh Computing demos advanced, scalable Video Analytics Solution portfolio at WWT’s Advanced Technology Center
Megh Computing’s Video Analytics Solution (VAS) portfolio implements a flexible and scalable video analytics pipeline consisting of the following elements: Video Ingestion Video Transformation Object Detection and Inference Video Analytics Visualization Because Megh’s VAS is scalable, it can handle real-time video streams from a few to more than 150 video cameras. Because it’s flexible, you can use the VAS pipeline elements to construct a wide range of video analytics applications such as: Factory floor monitoring to ensure that unauthorized visitors and employees avoid hazardous or secure areas Industrial monitoring to ensure that production output is up to specifications Smart City highway monitoring to detect vehicle collisions and other public incidents Retail foot-traffic monitoring to aid in kiosk, endcap, and product positioning, and other merchandising activities Museum and gallery exhibit monitoring to ensure that safe distances are maintained between visitors and exhibits Because the number of cameras can be scaled to well more than 100 when using the VAS portfolio, Megh clearly needed a foundational technology portfolio that would support the solution’s demanding video throughput, computing, and scalability requirements. Megh selected a broad, integrated Intel technology portfolio that includes the latest 3 rd Generation Intel® Xeon® Scalable processors, Intel® Stratix® FPGAs, Intel® Core™ processors, and the Intel® Distribution of the OpenVINO™ toolkit. Megh also chose WWT’s Advanced Technology Center (ATC), a collaborative ecosystem for designing, building, educating, demonstrating, and deploying innovative technology products and integrated architectural solutions for WWT customers, partners, and employees to demo the capabilities of the VAS. WWT built and is hosting a Megh VAS environment within its ATC that allows WWT and Megh customers to explore this solution in a variety of use cases, including specific customer environment needs and other requirements. For more information about the Megh VAS portfolio and the WWT ATC, check out the WWT blog here. Notices and Disclaimers Intel is committed to respecting human rights and avoiding complicity in human rights abuses. See Intel’s Global Human Rights Principles. Intel’s products and software are intended only to be used in applications that do not cause or contribute to a violation of an internationally recognized human right. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Intel technologies may require enabled hardware, software, or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.FPGA-Based Cloaking and Security Tech Helps Protect Equipment on IT and OT Networks from the Bad Guys
You can’t attack what you can’t see, and cloaking technology for devices on Ethernet LANs is merely one of many protection layers implemented in Q-Net Security’s Q-Box to protect networked devices and transaction between these devices from cyberattacks. Other security technologies built into the Q-Box include encryption, authentication, and the use of different, randomly generated security keys created just in time for each transaction – called JITKeys – with no external key management. Adding security to a networked device is as simple as placing a small Q-Box between a protected device and its LAN using an extra RJ45 cable. Each Q-Box can protect as many as 2000 network endpoints, allowing operators to create protected LAN segments throughout a larger network. Connect the Q-Box to a WAN router and the protected LAN segments can be located anywhere in the world. You can use the Q-Box to protect a wide range of networked devices including: Servers and PCs on IT networks Financial equipment ranging from ATMs in banks to slot machines in casinos Equipment connected to Operational Technology (OT) networks in buildings, factories, refineries, and utilities including PLCs and other industrial controllers, lighting systems, security systems and cameras, and even robotic equipment The Q-Box can secure any device on an Ethernet LAN. The Q-Box works with all networked devices including legacy systems. Face it. Cyberspace is getting more dangerous every day. Need proof? Here are just a handful of recent cyberattacks: December, 2020: Hackers inserted malicious code into SolarWinds’ Orion software, exposing sensitive and critical data at top government agencies including parts of the Pentagon, the Department of Homeland Security, the State Department, the Department of Energy, the National Nuclear Security Administration, and the Treasury; corporations including systems Microsoft, Cisco, Intel, and Deloitte; and other organizations including the California Department of State Hospitals, and Kent State University. 1 February, 2021: A Hacker attempted to poison the drinking water supply for Oldsmar, Florida by dangerously increasing sodium hydroxide levels in the water. 2 March, 2021: Hackers compromised more than 150,000 security cameras located in gyms, jails, schools, hospitals, and factories. 3 May, 2021: The DarkSide Russian hacking group forced Colonial Pipeline to cut the connection between its IT and OT networks, shutting down the company’s 5500-mile pipeline for several days and causing massive gasoline shortages on the US east coast. 4 Q-Net implemented the secure technology inside of the Q-Box using the programmable hardware in an Intel® Cyclone® FPGA. The Q-Box provides access protection without requiring changes or additions to an endpoint’s legacy code and with no modifications to existing equipment. In addition, the FPGA-based hardware in the Q-Box does not require and does not permit software updates or patches from the network. The network security protection it supplies is immutable. Because it’s implemented in hardware on an FPGA, the Q-Box introduces only a few microseconds of network latency. For more information about Q-Net Security’s Q-Box, click here. Notices and Disclaimers “SolarWinds Hack Victims: From Tech Companies to a Hospital and University,” The Wall Street Journal, https://www.wsj.com/articles/solarwinds-hack-victims-from-tech-companies-to-a-hospital-and-university-11608548402 “A Hacker Tried to Poison a Florida City's Water Supply, Officials Say,” Wired, https://www.wired.com/story/oldsmar-florida-water-utility-hack/ “Hackers just pulled off one of the most mind-boggling hacks of 2021 so far,” BGR Media, https://bgr.com/tech/security-cameras-hacked-verkada-customers-exposed/ “Intel® Agilex® FPGAs target IPUs, SmartNICs, and 5G Networks,” https://www.intel.com/content/dam/www/central-libraries/us/en/documents/agilex-fpgas-target-ipus-smartnics-5g-networks-white-paper.pdf Intel technologies may require enabled hardware, software or service activation. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Need to get Linux up and running on Intel® SoC FPGAs? These free “Ask the Expert” online sessions are for you
Do you have questions about using the Linux OS with FPGAs? Intel is holding another “Ask an Expert” session and the topic is “Using Linux with Intel® SoC FPGAs.” Come and ask our experts about the various Linux OS options available to use with the integrated Arm Cortex processors inside of Intel® SoC FPGAs. We’re ready to handle your questions about: Software development flow needed to create a Linux OS application Details for various supported Linux OS versions including latest stable kernels, the long term support initiative (LTSI), and LTSI with real-time patches How to build all the software pieces you’ll need when using the meta-Altera BSP recipe layer with either the Angstrom or Yocto distributions layers. The tools and platforms used in the embedded software development process including the RocketBoards community portal, Git, the Open Embedded build framework, and device trees. Whatever you would like to know about the using the Linux OS with Intel SoC FPGAs, come to this “Ask an Expert” session with your questions! During this “Ask an Expert” session you can come and ask questions, or you can discuss development techniques with other designers who are creating SoC FPGA designs and running Linux on the SoC. This is not a lecture-format Webcast where information only flows one way; It’s an interactive discussion with Intel technical experts who have hands-on experience with Linux and Intel SoC FPGAs. No matter what level of experience you have – everyone is welcome to come and ask questions. This “Ask an Expert” session will be run by Susannah Martin and Rod Frazer. Both are engineers with substantial experience with the subject matter. Susannah is a senior applications engineer in the customer training group for Intel FPGAs, FPGA high-level tools, as well as SoC-related content. Prior to becoming a trainer, she worked as an FPGA design engineer, embedded programmer, and field applications engineer. Rod has been an Embedded Technology Specialist FAE with Intel for over 20 years and has more than 35 years of industry experience in the embedded systems hardware and software development space. He has supported customer designs with the Nios® II soft processor, Intel SoC FPGAs, and the Intel FPGA tools used for embedded development including Platform Designer, System Console, Timing Analyzer, Signal Tap, as well as various embedded software development and debug tools for Intel SoC FPGAs. There will be two sessions to accommodate different geographies, so pick the session that best suits you: Wednesday, July 21, 2021 10:00AM – 11:00AM Pacific Daylight Time (17:00-1800 GMT) Wednesday, June 22, 2021 8:00AM – 9:00AM India Standard Time Click here to sign up for “Ask an Expert: Using Linux with Intel® SoC FPGAs,” We are finalizing our Ask an Expert topics for the rest of 2021. If there is any topic you would like covered, let us know! Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Win cash prizes in this year’s environmentally friendly, cloud connected InnovateFPGA design contest
InnovateFPGA contest sponsors – Terasic, Intel, Microsoft, Analog Devices, Arrow, Digi-Key, Mouser Electronics, and Macnica – invite ecologically minded teams to enter this year’s design contest to win cash prizes, medals, and fame. Competing teams will use the Terasic DE10-Nano FPGA Cloud Connectivity Kit with Analog Devices plug-in cards and IoT cloud connections provided by Microsoft Azure Cloud Services to create design solutions that help to reduce the environmental impact and the demands that we place on the Earth’s resources. All submitted projects must be based on and make complete use of the Intel® Cyclone® V SoC FPGA in the Cloud Connectivity Kit. The Terasic DE10-Nano FPGA Cloud Connectivity Kit with an Analog Devices plug-in card and credits/limited-time access to Microsoft’s Azure Cloud Services will be provided at no cost to selected participating teams. Contest teams will demo their designs at regional finals and at the Grand Finale, to be held in San Jose, California on June 23, 2022. Click here for more information and to enter the InnovateFPGA contest. Technical proposals are due by September 30, 2021. For full contest rules, click here. Get details on the Terasic DE10-Nano FPGA Cloud Connectivity Kit by clicking here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.BittWare announces IA-420F PCIe accelerator card and IA-220-U2 computational storage accelerator based on Intel® Agilex™ FPGAs and SoC FPGAs
BittWare has added two new accelerator products based on Intel® Agilex™ FPGAs and SoC FPGAs to the previously announced IA-840F Enterprise-Class FPGA Accelerator. (See “BittWare IA-840F FPGA Accelerator PCIe Card bristles with high-speed I/O, is based on an Intel® Agilex™ FPGA.”) The new IA-420F half-height, half-length, single-width PCIe card with multiple 100G network ports is designed for SmartNIC and computational storage applications and the IA-220-U2 computational storage processor in a U.2 form factor is specifically designed to accommodate NVMe computational storage workloads. BittWare provides all three FPGA-based accelerators with application reference designs and additional support for the Intel® oneAPI programming model, which provides hardware developers with the ability to create domain-specific FPGA platforms and allows application developers to build cross-architecture, single-source compilation designs. BittWare has added the IA-420F half-height, half-length, single-width PCIe card and the IA-220-U2 computational storage processor in a U.2 form factor to its existing line of workload acceleration products based on Intel® Agilex™ FPGAs and FPGA SoCs. According to BittWare, the IA-420F features a PCIe Gen4 x16 host interface that provides customers with as much as 2X the bandwidth normally available for FPGA-augmented systems, making it a compelling resource for accelerating data analytic workloads, while the IA-220-U2 can serve as a deployment-friendly computational storage processor in a U.2 NVMe storage array rack. For more information about these accelerators, please contact BittWare directly. For more information about the broad and growing line of Intel Agilex FPGA and SoC devices, click here, and be sure to read “Breakthrough FPGA News from Intel.” Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.APS Networks launches three OpenBNG Broadband Network Gateways incorporating Intel® Xeon® D processors, Intel® Tofino™ Switch ASICs, and Intel® Stratix® 10 MX FPGAs
Open BNG is an initiative within the Open Optical & Packet Transport (OOPT) Project Group’s Disaggregated Open Routers (DOR) sub-group, which is all part of the global Telecom Infra Project (TIP) that’s working to accelerate the development and deployment of open, disaggregated, and standards-based connectivity technology. TIP announced the initial release of the OpenBNG Technical Requirements document for large scale fiber-to-the-home (FTTH) networks – developed collaboratively by Telefónica, Deutsche Telekom, BT, and Vodafone – last October. The document encompasses: Hardware and software requirements for an open and disaggregated Broadband Network Gateway (BNG) device that operators can deploy in current and future networks for the provision of fixed broadband services (OpenBNG) The role of software-defined networks (SDN) and the desired approach for fixed-mobile convergence The required hardware and proposed non-mutually exclusive software packages needed to support additional services or functionalities Reference regulatory requirements to deploy Open BNG in the networks of the operators participating in the development of this requirements document The OpenBNG specification allows operators a choice of different hardware platforms and types of network operating system (NOS) and control-plane applications, with goals of lowering the total cost of ownership and lowering the cost per broadband subscriber. APS Networks has just launched three BNG switches which aim to comply with TIP OpenBNG requirements. Operators can choose among the SC-1, SC-2, and SC-3 TIP standard configurations for leaf designs that best address their end-user demands and cover both full-functionality deployments and service-only BNG deployments. The APS Networks® announcement includes three BNG products: The Hyperion APS2172Q, supporting 64x1/10/25G BNG user ports & 8x100G spine ports (SC-1) The Jupiter APS6120Q with 16x100G BNG ports & 4x1/10/25G ports (SC-2) The Hyperion APS2140D with 32x1/10/25G BNG user ports & 8x100G spine ports (SC-3 leaf) The APS2172Q and APS6120Q each support as many as 32,000 broadband subscribers and the APS2140D supports as many as 20,000 broadband subscribers. The announced BNG switches incorporate Intel® Xeon® D processors, P4-programmable Intel® Tofino™ Ethernet switch ASICs, and Intel® Stratix® 10 MX FPGAs with High-Bandwidth Memory (HBM). All BNG switch models can be equipped with a Precision Time Protocol (PTP) IEEE 1588v2 compliant add-on module, which enables the switches to operate as PTP boundary clocks with end-to-end accuracies of better than 10nsec. Andy Heal, Chief Technology Officer for APS Networks, said “The APS Networks range of OpenBNG switches accelerate the possibilities for access edge solutions. Combining these low latency products of Intel Tofino P4-programmable switch ASICs and Intel Stratix 10 MX FPGAs, with world-class PTP capabilities and Intel Xeon D processors, APS Networks have designed and developed a unique range of network switches for the wireline broadband market.” For more information about these APS Networks OpenBNG switches, please contact APS Networks directly. Click here. For more information about Intel Xeon D processors, click here. For more information about the Intel Tofino Ethernet Switch ASIC, click here. For more information about Intel Stratix 10 FPGAs including the Intel Stratix 10 MX FPGAs, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, Xeon, Tofino, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel at MWC: Panel Discusses “How is the O-RU reference architecture driving 5G Radio Development?”
Telecom operators need to reduce development time and while implementing new solutions to increase the performance and reliability of 5G networks in a cost-effective manner. Operators have already implemented open systems in their network cores and virtualizing functions, and now they want to achieve the same benefits with RANs including Radio Units (RUs). The Open RU (O-RU) roadmap covers both traditional macro radios and Massive MIMO and addresses key challenges including overall design cost reduction and accelerated time-to-market without sacrificing system-level power and performance. A 30-minute panel discussion about O-RU developments titled “How is the O-RU reference architecture driving 5G Radio Development?” in the Intel® Network & Edge Panel Series discusses the key digital, analog, RF technology, and business considerations that will enable radio ODMs, CMs, and System Integrators to offer flexible and scalable end-to-end RAN solutions. Panel participants include: Tero Kola, VP, System Product Management, Mobile Networks Business Group, Nokia Francisco (Paco) Martin, Group Head of OPEN RAN, Vodafone Rajesh Srinivasa, SVP and GM, Radio Business Unit, Mavenir Mike Fitton, VP, Intel Programmable Solutions Network Business Division, Intel Corporation Nitin Sharma, GM, Wireless Communications, Analog Devices, Inc (ADI) Moderator: Guy Daniels, Director of Content, TelecomTV Interested? Click here to watch the panel discussion. Click here to see all of the panel discussions in the Intel® Network & Edge Panel Series. Click here to see all the Intel events at Mobile World Congress. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Intel® Agilex™ FPGAs with high-performance Crypto Blocks target Infrastructure Processing Units (IPUs), SmartNICs, and 5G Networks
From the edge to the cloud, security challenges in the form of cyberattacks and data breaches loom ever larger as attacks on high-speed networks multiply. Massive amounts of data are at risk but so are physical resources including critical physical infrastructure. Cryptography and authentication represent potent countermeasures to these attacks. The latest members of the Intel® Agilex™ FPGA and SoC FPGA families (AGF023/AGF019 and AGI023/AGI019) now feature high-performance crypto blocks paired with MACsec soft IP to help mitigate the risks and limit the effects of these cyberattacks. Here’s a diagram showing the major features of these new Intel Agilex FPGAs with high-performance crypto blocks: A new White Paper titled “Intel® Agilex™ FPGAs target IPUs, SmartNICs, and 5G Networks” describes these Intel Agilex FPGAs with high-performance crypto blocks in more detail. For more information about Infrastructure Processing Units (IPUs), see: "Infrastructure Processing Units (IPUs) intelligently manage and accelerate data center infrastructure" "Want to know more about how Infrastructure Processing Units (IPUs) are revolutionizing data center architecture? A 4-minute video provides clarity" For more information about the broad and growing line of Intel Agilex FPGA and SoC devices, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Principal Industry Analyst Patrick Moorhead Explores Infrastructure Processing Units (IPUs) on Forbes.com
Navin Shenoy, Executive VP and GM for the Data Platforms Group at Intel, presented a vision for Infrastructure Processing Units (IPUs) earlier this week in a keynote speech titled "Why You Have Been Thinking About the Future of the Data Center All Wrong" at The Six Five Summit, a strategy event presented by Patrick Moorhead’s company, Moor Insights & Strategy, and Futurum Research. That same day, Moorhead published a detailed article about Shenoy’s keynote and IPUs titled “Intel Announces The 'Infrastructure Processing Unit' At The Six Five Summit 2021” on Forbes.com. In the article, Moorhead wrote: “So, what is an IPU? An IPU is designed to offload the main CPU in the datacenter and edge, which gives more predictable and efficient application performance and enables improved virtualization capabilities that CSPs and carriers are seeking.” A bit later in the article, he wrote: “Micro-services are a way to have your cake and eat it too, as you can run them at the most efficient place but keep a sense of management through orchestration. That orchestration, as I will dig into later, creates challenges that an IPU can help solve.” He discusses some alternatives and then asks: “But what makes Intel’s IPU different?” And he immediately answers his own question: “Intel knows the data center and says it’s the only IPU built in collaboration with hyperscale cloud partners. This would mean that Intel would be able to actively innovate and deliver a product that is already addressing real-world problems. Technically, if you equate its SmartNIC as IPU, Intel is already the IPU volume leader in the IPU market with Xeon-D, FPGA and Ethernet components.” There’s more detail in the Forbes.com article. Click on the link above to read it in full. For more information about Infrastructure Processing Units (IPUs), see “Infrastructure Processing Units (IPUs) intelligently manage and accelerate data center infrastructure” and “Want to know more about how Infrastructure Processing Units (IPUs) are revolutionizing data center architecture? A 4-minute video provides clarity.” Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Want to know more about how Infrastructure Processing Units (IPUs) are revolutionizing data center architecture? A 4-minute video provides clarity
Yesterday, Intel unveiled its vision for infrastructure processing units (IPUs), programmable networking devices that free up CPU cycles by taking over and intelligently managing system-level infrastructure in data centers. (See “Infrastructure Processing Units (IPUs) intelligently manage and accelerate data center infrastructure.”) The company also announced that IPUs based on Intel® CPUs and Intel® FPGAs are already shipping from Intel and Intel Partners. You can find out more about IPUs from Intel and Intel Partners by clicking here. If you’d like a deeper dive into IPUs and their application, Guido Appenzeller, chief technology officer with Intel's Data Platforms Group, has made a 4-minute video giving a concise and easily understood explanation of the IPU concept. You can watch the video here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
