srinivasan
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Pcie loopback in the root complex mode
Hello sir, Please share the reference design for pcie loop back in the root port mode. Pcie root complex act as master and end point act as slave. End point should enter into loop back mode.(TS1 loop bit need to set).But i dont know how to access in the design.so please share the root port loop back reference design.946Views0likes0CommentsRe: Pcie loopback in the end point
Thanks for the reply, Hello chuan, What you shared is correct, but I want to send the loopback configuration packet from the root complex design to end point. Please send the screenshot of the loopback register used in the implemented root complex design. Note: End point should be in loopback mode4KViews0likes2CommentsPcie loopback in the end point
Hello sir, I am using Arria 10 Pcie Hard IP in Arria 10 SOC development kit , Here I am configuring IP as Pcie root complex (Master FPGA) and need to acheive the loop back mode at the end point(other device). For that I need to configure the TS1 Loopback bit set in the root complex to enable loop back mode at the end point. Here My query is how/where I need to set the TS1 loopback bit in the Pcie root complex design to enable loop back at the end point.So Please share me the Corresponding Registers and steps need to be followed in the Design. If possible please share the End point loop back and root complex reference design. Regards, Srinivasan.4.1KViews0likes14CommentsEMIF compile issue
Error(16614): OCT Block "emifchk_inst|emif_0|emif_0|arch|arch_inst|oct_inst|cal_oct.powerup_oct_cal.termination_inst" cannot terminate pins "O_FPGA_MEM1_A(0)~pad" and "IO_FPGA_MEM1_DQ(0)~pad" because they have different series termination values: "40 Ohms" and "34 Ohms" respectively. Change your pin assignments so that only pins with the same series termination value are connected to an OCT block. Can anyone give solution for above error..918Views0likes2CommentsEMIF FPGA IP compilation error
Hi, I am using external memory interface intel fpga ip.In that I am getting error when I integrated EMIF ip in my top module... But when I compiled the EMIF IP alone..I am not getting any error While I added that IP in my top...I am facing below error... Error (17045): Input port I of I/O input buffer primitive |emif_0| .. |gen_mem_alert_n.inst[0].b|no_oct.ibuf is not connected Can anyone please give me solution for above error...891Views0likes3CommentsModelsim license issue
Hi, I am facing license error in model sim... Error: cannot find license file Error:Failure to obtain license. But I have loaded my license file in quartus tool..I can able to compile my code also... But modelsim showing such error...is there any setting need to change??... Can anyone please help on this??1KViews0likes2Comments