jackgreen
New ContributorJoined 5 years ago
User Profile
New Contributor
User Widgets
Contributions
OpenCL Host-to-Memory Read Speed varies in linux kernels
Board: Teriasic De10 Nano OpenCL for FPGA standard 18.1 Hi everyone, I am working on a project on De10 nano using OpenCL. I ran an official board test program from Terasic on two OS. One is the official img from Terasic and got a Host-global-memory read speed of 155 MB/s The other one is on a linux kernel 4.19 with Ubuntu and got a Host-global-memory read speed of 60 MB/s. Does anyone know are there any configurations in kernel complication that would affect the Host-global-memory read speed? The boardtest reports are attached. Thanks in advance!Re: FPGA Opencl caching for CPU access to shared memory through ACP port
Thanks for your reply! However, I am satisfied with the performance of the kernel right now. And I really want to optimize the process where data is transferred to and from the shared memory. It costs much more time than the kernel running.FPGA Opencl caching for CPU access to shared memory through ACP port
I am doing a project on CycloneV soc which involves transferring large amount of data from memory to FPGA. As DMA needs to work with physically contiguous memory, I copied data to the share memory first (allocated by clEnqueueMapBuffer) and then FPGA consumes the data accordingly. The problem I am having now is that moving data to the shared memory in user space is very time-consuming. I think it is due to the fact that Intel OpenCL library disables the caching for cpu access to the shared memory (as shown in the following pic). I can understand that it's hard to manage cache coherence in this case but it is not impossible to achieve! As the Intel OpenCL library is not open-source, it seems hard for us to do any changes and enable the cache. Can anyone tell me a way around this problem, plz?Re: OpenCL multi-thread error: HAL Kern Error: Read failed from addr 20
Not sure how many active users are still using this forum. For what is worth, I want to share my results for solving this problem. Hope this could help people who come across the same problem. The problem indeed lies in the MMD library. In all current version of csoc5 BSPs and RTEs, Version 14.1 MMD is used. The newest MMD is of version 18.1 which I found in Intel Opencl FPGA SDK Pro 20.4. Seems like this version was just resleased. In the MMD 18.1, it mentioned in the source file about fixing this bug in 14.1. // global variables used for handling multi-devices and its helper functions // Use a DeviceMapManager to manage a heap-allocated map for storing device information // instead of using a static global map because of a segmentation fault which occurs in // the following situation: // 1) Host program contains a global variable which calls clReleaseContext in its destructor. // When the program ends the global goes out of scope and the destructor is called. // 2) clReleaseContext calls a function in the MMD library which modifies the static global map in // the MMD library. // In this situation it was discovered that the destructor of the static global map is called before // the destructor of the global in the host program, thus resulting in a segmentation fault when // clReleaseContext calls a function that modifies the internal map after it has been destroyed. // Using a heap-allocated map avoids this issue as the lifetime of the map persists until it is // deleted or the process is completely terminated. So when I remove my global variables, everything works.Re: Getting "HAL Kern Error: Read/Write failed from addr x, read y expected z" when running multithread OpenCL application on CycloneV SoC
Hi I am having a similar problem on the de10 nano board. After checking the corresponding source code, I found out that the MMD library is of version 14.1 and it does not have AOCL_MMD_CONCURRENT_READS and AOCL_MMD_CONCURRENT_WRITES defined. So I guess it might be the problem? And how shall we update this library? Is there any off-the-shelf code I could takeRe: Getting "HAL Kern Error: Read/Write failed from addr x, read y expected z" when running multithread OpenCL application on CycloneV SoC
Hi I am having a similar problem on the de10 nano board. After checking the corresponding source code, I found out that the MMD library is of version 14.1 and it does not have AOCL_MMD_CONCURRENT_READS and AOCL_MMD_CONCURRENT_WRITES defined. So I guess it might be the problem? And how shall we update this library? Is there any off-the-shelf code I could take advantage of? Thanks!OpenCL multi-thread error: HAL Kern Error: Read failed from addr 20
Platform: terasic De10-nano (CycloneV soc) Software version: OpenCL SDK 18.1, MMD version 14.1 Problem description: I am developing an application using multi-thread (while only one thread will run NDRange and execute the FPGA kernel) and got this error: HAL Kern Error: Read failed from addr 20, read -1237012464 expected 4 HAL Kern Error: Read failed from addr 20, read -1237012464 expected 4 HAL Kern Error: Write failed to addr 1000 with value 0, wrote -1237012464 expected 4 HAL Kern Error: Write failed to addr 20 with value be80a2dc, wrote -1237012464 expected 4 Sometimes the program will be killed and sometimes will not. I suspect it may due to multi-thread somehow, so I test the intel official example multithread_vector_operation (which is attached) A similar error comes out but with only read failed. HAL Kern Error: Read failed from addr 20, read -1234415600 expected 4 I used gdb to debug this and found out the SIG44 was received when two threads were at clWaitForEvents(). I notice that someone already asked a similar question and mentioned that it may be due to the obsolete MMD library. But I saw that all csoc5 RTE are with MMD 14.1. Can anyone shed a light on this problem, please? Thanks in advance!
