AndyRea
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ASMI Page Write
using an Arria 10, MT25QU256 flash and ASMI erase and single byte write work fine however the page write of either 4 or 256 bytes both appear to fail / not do what the user guide says it should having tapped the IP core signals directly, i am bursting in 4 bytes at a time using the shift_en signal and wren as can be seen in the picture, the busy strobe goes high 1 clock cycle after the first write cycle, not at the end of the burst when the write strobe is applied core is set up for the flash chip using a jic and quartus programmer, the device works perfectly and programs the flash which can then boot the card no issue erasing with ASMI works fine, as does reading the flash back out using quartus 19.1 with the ini file patch for the MT25x devices but still no joy what am I missing here as its driving me mad now!?simulate parameterized ip block dcfifo_mixed_widths
using this as a verilog module included in a design inside a vhdl wrapper, how do i get modelsim to pick up the dcfifo_mixed_widths ip block properly so it can run testbenches? // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module parametrized_fifo# ( parameter DATA_WIDTH=64, parameter NUM_OF_WORDS=256, parameter ALM_FULL_VAL=6, parameter USEDW_ADDR_WIDTH=8 // log2 of NUM_OF_WORDS ) ( aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw, almost_full); input aclr; input [DATA_WIDTH-1:0] data; input rdclk; input rdreq; input wrclk; input wrreq; output [DATA_WIDTH-1:0] q; output rdempty; output [USEDW_ADDR_WIDTH-1:0] rdusedw; output wrfull; output [USEDW_ADDR_WIDTH-1:0] wrusedw; output almost_full; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 aclr; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif wire [DATA_WIDTH-1:0] sub_wire0; wire sub_wire1; wire [USEDW_ADDR_WIDTH-1:0] sub_wire2; wire sub_wire3; wire [USEDW_ADDR_WIDTH-1:0] sub_wire4; wire [DATA_WIDTH-1:0] q = sub_wire0[DATA_WIDTH-1:0]; wire rdempty = sub_wire1; wire [USEDW_ADDR_WIDTH-1:0] rdusedw = sub_wire2[USEDW_ADDR_WIDTH-1:0]; wire wrfull = sub_wire3; wire [USEDW_ADDR_WIDTH-1:0] wrusedw = sub_wire4[USEDW_ADDR_WIDTH-1:0]; wire sub_wire5 = wrusedw[USEDW_ADDR_WIDTH-1]; assign almost_full = sub_wire5; dcfifo_mixed_widths dcfifo_mixed_widths_component ( .aclr (aclr), .data (data), .rdclk (rdclk), .rdreq (rdreq), .wrclk (wrclk), .wrreq (wrreq), .q (sub_wire0), .rdempty (sub_wire1), .rdusedw (sub_wire2), .wrfull (sub_wire3), .wrusedw (sub_wire4), .eccstatus (), .rdfull (), .wrempty ()); defparam dcfifo_mixed_widths_component.add_usedw_msb_bit = "ON", dcfifo_mixed_widths_component.enable_ecc = "FALSE", dcfifo_mixed_widths_component.intended_device_family = "Arria 10", dcfifo_mixed_widths_component.lpm_hint = "DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT=TRUE", dcfifo_mixed_widths_component.lpm_numwords = NUM_OF_WORDS, dcfifo_mixed_widths_component.lpm_showahead = "OFF", dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths", dcfifo_mixed_widths_component.lpm_width = DATA_WIDTH, dcfifo_mixed_widths_component.lpm_widthu = USEDW_ADDR_WIDTH, dcfifo_mixed_widths_component.lpm_widthu_r = USEDW_ADDR_WIDTH, dcfifo_mixed_widths_component.lpm_width_r = DATA_WIDTH, dcfifo_mixed_widths_component.overflow_checking = "ON", dcfifo_mixed_widths_component.rdsync_delaypipe = 5, dcfifo_mixed_widths_component.read_aclr_synch = "OFF", dcfifo_mixed_widths_component.underflow_checking = "ON", dcfifo_mixed_widths_component.use_eab = "ON", dcfifo_mixed_widths_component.write_aclr_synch = "OFF", dcfifo_mixed_widths_component.wrsync_delaypipe = 5; endmoduleip-setup-simulation custom ip components
running ip-setup-simulation to create a top level set of sim files, fails with a lot of these messages Error: 2022.02.10.10:43:27 Error: SPD file C:/final/xxxxx/alt_clk_for_cdr\alt_clk_for_cdr.spd not found. Please generate simulation files for IP file C:/final/xxxxx/alt_clk_for_cdr.ip before generating simulator setup scripts. i have no ability to actually create sim scripts for all thee IP blocks ( some are part of a JESD example project and some are custom ip componets I've written ) i dont actually want to simulate any of the chunk that fail as they are mainly part of a PCIe backend that i can emulate in a different way for the purposes of test benches how do i work around this?Arria 10 Simulations with ModelSim
i am trying to use modelsim to simulate some chunks of a VHDL design which now include some FIFO modules ( the design also has PCIE, JESD cores and a whole bunch of other stuff ) I can compile the modules in modelsim ok until i get to modules that refer to the FIFO ip blocks ( the whole design compiles & fits fine in Quartus so is ok a a "thing" ) when I try and run the "Generate Simulator Setup Script for IP" and point it at the root of the project, it runs through but then complains that a bunch of modules in the PCIe back end do not have simulation profiles and fails to complete along the lines of Error: 2021.11.08.14:21:15 Error: SPD file C:/final/pcie_ips/pcie_a10_hip_0_example_design/ip/pcie_example_design/fast_dac_onchip_ram_1\fast_dac_onchip_ram_1.spd not found. Please generate simulation files for IP file C:/final/pcie_ips/pcie_a10_hip_0_example_design/ip/pcie_example_design/fast_dac_onchip_ram_1.ip before generating simulator setup scripts. but that actual entity is a custom created module wrapped around a DP RAM module so doesnt have any simulation options I know i don't need to do the simulation library compiler thing as the twentnm library etc is there for the Arria 10 devices but I think until i can get the simulator script to run then I'm stuck on getting the FIFOs to be compiled in modelsim. I did try manually trying to compile the bits I could see in the relevant sim folders where the FIFO instances were created directly in modelsim but couldnt get it happy i would like not have to try and re-create a new project with the relevant source in it just to try and exclude these failing modules, so wondering if anyone has any pearls of wisdom of how to essentially exclude chunks of the design from the simulation script generator or something that will get me a running sim ? thanks AndyPCIE surprise removal BIOS crash when reprogramming
using an Arria 10 with Hard PCIe engine for a DMA application with Ubuntu 20.x Linux as the host OS when the card is in a newish HP machine, re-programming the FPGA through JTAG once installed and running in the machine causes an instand PCIE surprise down type low level crash which needs a key press to then resume booting older gigabyte machine didn't care so was ok but now that died and am stuck with the HP G4 PC and this issue, it's a bit boring with essentially having to keep the flash boot un-programmed and then having : shutting the machine down, starting it up, booting, JTAG program and reboot to then be able to reload the kernel driver and start the next tests. Does anyone have an easier way of getting past the BIOS PCIe exception or thoughts? I dont think there are any things I can do in Linux as it seems to be lower levle than this and i have crawled all through the BIOS settings but found nothing that seems to make a difference enabled or disabled there must be an easier way of PCIe dev than this?! thanks for any suggestions Andy
