ContributionsMost RecentMost LikesSolutionsRe: Cyclone 10 GX ATX PLL questions Hi Farabi, Sorry for the delay in responding to your reply. Regarding bandwidth settings, thank you for that explanation, and I accept your answer. Regarding my questions on Section 3.1.1, I don't think you answered them; however, you did provide the context for when the rules must be followed. I'll just restate the questions: Section 3.1.1 of the "Transceiver PHY User Guide" version 20.1, specifies that "ATX PLLs' VCO frequency offset must be 100 MHz apart". What is "frequency offset" in this context? Is this the same thing as "PLL output frequency"? Will Quartus provide a warning or error if I violate this rule? We do have designs that instantiate multiple PLLs, and we intend to perform recalibration, so I want to make sure I fully understand the rules on separation. Thank you. Cyclone 10 GX ATX PLL questions Hello, Two questions regarding Cyclone 10 GX ATX PLLs: 1) When configuring the ATX PLL in Quartus Prime Pro 21.4 IP Parameter GUI, there is a field for VCO bandwidth. I can set this as low, medium, and high. Where can I find guidelines on the best setting to use for my particular configuration? 2) Section 3.1.1 of the "Transceiver PHY User Guide" version 20.1, specifies that "ATX PLLs' VCO frequency offset must be 100 MHz apart". What is "frequency offset" in this context? Is this the same thing as "PLL output frequency"? Will Quartus provide a warning or error if I violate this rule? Thank you. Re: Questa Design Optimization Box has OK Disabled Hello, I'm still hoping for a reply / solution to this issue. Thank you. Re: Questa Design Optimization Box has OK Disabled Please see attached screen shot. Clicking OK does nothing. Clicking Cancel returns "# Optimization canceled" in the console. Thank you Questa Design Optimization Box has OK Disabled Hi, I'm new to Questa, and I'm trying to change the visibility options available in the Design Optimization Box. However, the OK button is disabled, so I can't make any changes. I have tried it before and after simulation is started. I'm using it on Ubuntu 18.04 as part of the Quartus 21.3 release. I'm using the Intel Starter Edition. What am I doing wrong? Thanks How to obtain a Questa license when using Quartus Pro 21.3 without a license? Hello, I have just installed Quartus Pro 21.3 to use with Cyclone 10 GX (free license), but I'm not sure how to get a Questa (Intel Starter Edition) license. I have visited the Self Service Licensing Center, but it seems that I can't do much there without a valid license. Please let me know how I should obtain a Questa license for my use case. Thank you SolvedRe: Modelsim: "Unable to replace existing ini file" Yes, it simulates fine. The problem is when I try to compile even a simple Verilog file. That's when Modelsim hangs and I see the console errors. I'm just living with it for now. Re: How do I pick up altera_a10_xcvr_clock_module in a Cyclone 10 GX Modelsim Simulation? Thank you for the reply. I wasn't able to find the library for altera_a10_xcvr_clock_module. However, since it provides no functionality to a simulation, the simplest path forward was to define it out with our SIMULATION directive. Re: Modelsim: "Unable to replace existing ini file" I should have mentioned that I had already tried reinstalling it. It didn't make a difference. Thank you. Re: Modelsim: "Unable to replace existing ini file" Thank you for the reply. The "sim" folder is OUTSIDE the C:\intelFPGA_pro installation folder. As an authenticated user, I have full control over my "sim" folder. Also, I have verified the *.mpf file is NOT set for read only.