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LH12

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Joined 5 years ago

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Re: Stratix V 5SGXMA3K3F40C4 IHS sealant
We'll be using it vacuum and it requires low outgassing property. If you have spec on the FPGA outgassing parameters that will be helpful thx
5 years ago Place FPGA Device
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Stratix V 5SGXMA3K3F40C4 IHS sealant
We're planning to use Stratix V, 5SGXMA3K3F40C4, in extreme environment. Question : Is the sealant between the IHS/lid and the die/substrate hermetically sealed? thx
5 years ago Place FPGA Device
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FPGAs arrived in jedec trays instead of vacuum pack
I've received few batches of FGPAs from PSG through arrows in jedec trays instead of vacuum packs. What is the risk of storing these parts for the next 24 months ? Is baking a solution for this parts?
5 years ago Place FPGA Device
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Ultra low voltage IO pins support on 5SGXMA3K3F40C4
Can Stratix5 support low voltage IO at 0.55V ?
5 years ago Place FPGA Device
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200MHz on 5SGXMA3K3F40C4
We re trying to enable 200Mhz single ended IO. Would like to seek some technical support on how to enable this. On the same topic, what is the risk of running with 200MHz on a large qty of FPGAs. Will there be a risk due to binning issue? And is there a recommended drop in upgradable parts from our current FPGA, 5SGXMA3K3F40C4, to another with capability of clock speed up to 400MHz
5 years ago Place FPGA Device
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Question on 5SGXMA3K3F40C4 DDR3 IP
We implement DDR3 IP on the device and saw some stability issues between FPGAs of the same type. Some FPGA works fine while some is not working even though the same firmware is being used. Would like to understand more about this observation to see how we can create a more stable firmware.
5 years ago Place IP & Transceiver
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