Hidetaka
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Re: fitter error in Quartus Prime Pro 25.1.0.
Hello, sstrell-san. This has been resolved for now, so you may close this case. Personally, I thought it would be better if Quartus would automatically set Data[0] to "Use as regular I/O" when I selected Active Serial in the Configuration scheme. Thanks, Hidetaka.Re: fitter error in Quartus Prime Pro 25.1.0.
Hello, sstrell-san. Your message gave me a hint. When I looked at the Dual-Purpose Pins setting, I saw that Data[0] was in Dual-Purpose Pins. This is my first time using the Cyclone 10GX, and in the Flex10K and other Cyclone families that I have used up until now, AS_Data0 and Data[0] were assigned to the same pin, so I assumed they were the same. When I set DATA[0] to "Use as regular I/O", I was able to compile without errors. By the way, this is the board we will be using this time. https://www.hdl.co.jp/ACM-115L/ This board was first released in March 2019, but it seems that the Enpirion power supply IC was discontinued and replaced with a new one, resulting in the current version. Thanks, hidetaka.Re: fitter error in Quartus Prime Pro 25.1.0.
Hello, sstrell-san. I don't think you've correctly understood my inquiry. I'm assigning a signal to Pin_AE5. I'm getting a message saying that the Quartus Fitter cannot assign that pin to "~ALTERA_DATA0~". However, "~ALTERA_DATA0~" for this device should be Pin_Y4. The fitter pin is clearly wrong. There is an error in the device data used by the fitter. I think the problem is on the Quartus fitter side. Incidentally, the configuration scheme is AS mode. Regards, Hidetaka,fitter error in Quartus Prime Pro 25.1.0.
Hello, I am having trouble with a fitter error in Quartus Prime Pro 25.1. set_global_assignment -name DEVICE 10CX105YF672I5G I purchased a board with a 10CX105YF672I5G mounted on it, and am creating an FPGA design. The tool I am using is Quartus Prime Pro 25.1.0. I am assigning a user pin to Pin_AE5 in the design I am creating, but the fitter is displaying the following error message: "Pin ~ALTERA_DATA0~ is assigned to pin location Pin_AE5 (IOPAD_X38_Y17_N61)" However, Pin ~ALTERA_DATA0~ for this device should be Pin_Y4. I think the pin information the fitter is using is incorrect. Please let me know if there is a solution. Regards, HidetakaRe: Problem with Quartus prim standard 24.1: I cannot generate IP for the hardware memory controller of
Hello Richard-san, I had another issue in the Support Community. I added "TBB_MALLOC_DISABLE_REPLACEMENT=1" to the system environment variables that Adzim-san told me about, and was able to generate the Example Design without any errors. See here. I am unable to generate the Cyclone VGX LPDDR2 controller IP due to an error. - Intel Community I am very grateful to you. Please close this issue.Re: I am unable to generate the Cyclone VGX LPDDR2 controller IP due to an error.
Hello Adzim-san, I added "TBB_MALLOC_DISABLE_REPLACEMENT=1" to the system environment variables you told me about, and was able to generate the Example Design without any errors. I'm very grateful to you. Please close this case here. Thanks, Hidetaka.Re: Problem with Quartus prim standard 24.1: I cannot generate IP for the hardware memory controller of
Hello, Richard-san. I uninstalled Quartus Prime standard 24.1 and then reinstalled it. I did not install CDT8.8.1 and generated the LPDDR2 IP again. The result was the same; an error occurred when checking "Generate Example Design". If I uncheck it, generate completed successfully. For the time being I will continue development without checking "Generate Example Design", but I would like this to be improved. ////////// error message Error: Execution of script C:/Users/xxxx/AppData/Local/Temp/alt0224_5461300254259846718.dir/0008_LPDDR2_top2_gen/simulation/generate_sim_example_design.tcl failed ///////// Regards, Hidetaka.
