RFett
New ContributorJoined 6 years ago
User Profile
New Contributor
User Widgets
Contributions
PCIe example program on Cyclone 10CX105YU484
Quartus 19.3 / Intel provides a sample design pcie_ed with a pcie IP connecting to a simple RAM. It runs properly on the Development Kit for Cyclone 10 with a 2 lane gen 2 configuration, 64 bit @ 125MHz. I have a design based on 10CX105YU484. This board gets properly enumerated using the same design. The provided device driver (altera_pice_win_driver / Altera PCI API Driver) is loaded on my Windows 10 x64, no issue is shown. Running the Interop_software Alt_Test.exe on this board failes. Using my own driver which works with the Dev Kit, shows that only 0xffffffff can be read back. Since the board is enumerated I assume the PCIe IP is partially working. Routing out the Avalon chipselect and write signals to test points do not show any activity. While on the Dev Kit I can properly measure these control signals. The entire design relies on IPs from Intel, I wonder what I am missing. Any suggestion were to go from here would be very much appreciated.Re: Error on attempt to download sof and jic file to Cyclon 10GX dev. board using JTAG. How to proper setup to get jic file programmed to EPCQL1024?
Hello John I was able to download the jic to the device. Thank you for this. Correct me if I am wrong: if I includ the flash loader ip into my design, after power up the programmer should recognize the epcql1024 when scanning the chain? Thank you! RolandRe: Error on attempt to download sof and jic file to Cyclon 10GX dev. board using JTAG. How to proper setup to get jic file programmed to EPCQL1024?
Hello John I seem to miss something. Obviously I took the c10gx_sss.sof file found in the build_factory_source folder. What you are telling me is this is not the right image to take? How to choose the "right" design to do so? Thank you! RolandRe: Error on attempt to download sof and jic file to Cyclon 10GX dev. board using JTAG. How to proper setup to get jic file programmed to EPCQL1024?
Hi John Thank you for your prompt answer. I tried to download as proposed and I am afraid it did not work. See screenshot below. A very worring thing is the readme file in the factory_recovery folder, containing the following sentence: "Note: .jic file cannot be programmed via Quartus Prime Programmer at this moment, will be fixed later in v18.0 or later build." Is this working indeed now?Error on attempt to download sof and jic file to Cyclon 10GX dev. board using JTAG. How to proper setup to get jic file programmed to EPCQL1024?
Using the C10 CVP sample project I added the Serial Flash Loader IP to the design into the top_hw.v. I setup the jtag chain for the Cyclon 10 GX Dev. Kit, download the 10 design (sof) -> ok and download of the jic file starts -> error Flash Loader IP not loaded on device 3. AS is enabled (S1.x default). Unlike with other designs detecting of the jtag chain does not show the epcql1024. The cyclon 10 design is loaded with the right jtag usercode, as a try.
