서박사
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Memory Access from both HPS and FPGA
Hello, I'm quite new to embedded programming so please excuse me if the question is quite simple and unrefined. I'm trying to build a system with HPS, containing memory. Especially, the system targets to read the data from the SD card, write the data to temporary memory, and send the data in a serial manner to GPIO extension port (JP1). At first, since I'm not familiar with the embedded system, I've tried to use the demonstration from the university program (DE1-SoC_Computer) and configured my system as follows: The operation I've intended is as follows: ① Send the data to the board (or give a command to a terminal to read the data from SD card) ② The data transfers to the ARM core through the interface and the bridge between HPS-FPGA ③ Transferred data is stored to DDR3 DRAM, which is located at HPS side ④ Give a command to a terminal to send the data to GPIO port ⑤ The command is also transferred through a bridge ⑥ The data is read from DDR3 DRAM ⑦ The read data is transferred to GPIO port However, I found that ④-⑤-⑥-⑦ takes at least 500ns and thus limits the data rate at the GPIO port. (especially, alt_write_word function takes 500ns) So now I want to revise the system as follows: The operation I want is as follows: ① Send the data to the board (or give a command to a terminal to read the data from SD card) ② The data transfers to the ARM core through the interface and the bridge between HPS-FPGA ③ Transferred data is stored to SDRAM, which is located at FPGA ④ Give a command through PIO, to fetch the data from SDRAM to FIFO (or on-chip SRAM?) ⑤ The data is fetched from SDRAM to FIFO ⑥ The fetched data is transferred to GPIO port From the above situation, I have the following questions: 1. Is the revised system configuration is practical to be implemented? (i.e. can we build a system like the later figure using the DE1-SoC?) 2. May I improve the data rate with the revised configuration of the system? 3. I'm currently stuck at the ⑤ since I don't know how to access the data to SDRAM from the FPGA side, which data bus is currently connected to multiple Avalog-MM masters at NIOS II and AXI master at HPS. I'm trying to add a DMA controller at the system configuration and connect the read_master to the data bus, but I'm not sure about the desired operation. Are there any demos or examples that I can refer to? I'm sorry for the unrefined questions and information since I'm even not sure that I'm asking an appropriate question. If you need any additional information on the configurations above, please let me know. Thank you!
