Sopc2DTS with Agilex 7
After generating a qsys_top.sopcinfo with quartus for the SocFPGA Agilex 7 design, i'm trying to get the .dts then the .dtb from it via sopc2dts. I'm encountring the following issue: $ java -jar sopc2dts.jar --input ../Bureau/qsys_top.sopcinfo --output essai_libs.dts --type dts --extra-component-libs sopc_components_altera.xml --extra-component-libs sopc_components_fps.xml --extra-component-libs sopc_components_labx.xml --extra-component-libs sopc_components_others.xml Unsupported interface kind: ftile_hssi_system_clock_source Unsupported interface kind: ftile_hssi_reference_clock_source Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_reference_clock_sink Unsupported interface kind: ftile_hssi_system_clock_sink ... Unsupported interface kind: ftile_hssi_system_clock_source Unsupported interface kind: ftile_hssi_reference_clock_source Component agilex_hps of class intel_agilex_hps is unknown Component emif_cal_0 of class altera_emif_cal is unknown Component emif_cal_1 of class altera_emif_cal is unknown Component emif_fpga of class altera_emif_fm is unknown Component emif_fpga_1 of class altera_emif_fm is unknown Component emif_hps of class altera_emif_fm_hps is unknown Component mm_ccb_0 of class mm_ccb is unknown Component mm_ccb_1 of class mm_ccb is unknown Component qsys_top_mux_ddr0 of class mux_ddr0 is unknown Component qsys_top_mux_ddr1 of class mux_ddr0 is unknown Component user_rst_clkgate_0 of class altera_s10_user_rst_clkgate is unknown Component agilex_hps of class intel_agilex_hps is unknown Component emif_cal_0 of class altera_emif_cal is unknown Component emif_cal_1 of class altera_emif_cal is unknown Component emif_fpga of class altera_emif_fm is unknown Component emif_fpga_1 of class altera_emif_fm is unknown Component emif_hps of class altera_emif_fm_hps is unknown Component mm_ccb_0 of class mm_ccb is unknown Component mm_ccb_1 of class mm_ccb is unknown Component qsys_top_mux_ddr0 of class mux_ddr0 is unknown Component qsys_top_mux_ddr1 of class mux_ddr0 is unknown Component user_rst_clkgate_0 of class altera_s10_user_rst_clkgate is unknown Component agilex_hps of class intel_agilex_hps is unknown Component emif_cal_0 of class altera_emif_cal is unknown Component emif_cal_1 of class altera_emif_cal is unknown Component emif_fpga of class altera_emif_fm is unknown Component emif_fpga_1 of class altera_emif_fm is unknown Component emif_hps of class altera_emif_fm_hps is unknown Component mm_ccb_0 of class mm_ccb is unknown Component mm_ccb_1 of class mm_ccb is unknown Component qsys_top_mux_ddr0 of class mux_ddr0 is unknown Component qsys_top_mux_ddr1 of class mux_ddr0 is unknown Component user_rst_clkgate_0 of class altera_s10_user_rst_clkgate is unknown Component xcvr_12a_bank_systemclk_f_0 of class systemclk_f is unknown Component xcvr_12a_bank_xcvr_12a_fmc_quad2 of class directphy_f is unknown Component xcvr_12a_bank_xcvr_12a_fmc_quad3 of class directphy_f is unknown Component xcvr_12a_bank_xcvr_12a_qsfp of class directphy_f is unknown Component xcvr_13a_qsys_fmc of class directphy_f is unknown Component xcvr_13a_qsys_qsfp1 of class directphy_f is unknown Component xcvr_13a_qsys_systemclk_f_0 of class systemclk_f is unknown Component xcvr_13c_qsys_fmc of class directphy_f is unknown Component xcvr_13c_qsys_systemclk_f_0 of class systemclk_f is unknown Unable to find a master of type CPU. Randomly selecting the first master we find (agilex_hps). How to fix this and have a complete and correct device tree that can be compiled into .dtb? I'm working with agilex 7. + if i wanna custom an OS and do it in the HPS of my board (like adding new modules using gpios), is it mandatory to add some blocks in the .dts ?
sopc2dts Errors
These are the errors showing when I run the sopc2dts command. I am using DE10 Standard FPGA. I have stored dtb files earlier with the image file on an sdcard and the FPGA loads well. However, the dtb generated with this doesn't work with the image file. Kindly help resolve these. $ sopc2dts --input hps_ethernet.sopcinfo --output socfpga.dtb --type dtb --board soc_system_board_info.xml --board hps_common_board_info.xml --bridge-removal all --clocks Component System_PLL of class altera_up_avalon_sys_sdram_pll is unknown Component System_PLL of class altera_up_avalon_sys_sdram_pll is unknown Component System_PLL of class altera_up_avalon_sys_sdram_pll is unknown Component System_PLL of class altera_up_avalon_sys_sdram_pll is unknown Point of view: 'hps_0_arm_a9_0' could not be found. Trying to find another one. DTAppend: Unable to find parent, null, for n25q512a@0. Adding to root DTAppend: Unable to find parent, null, for next-level-cache. Adding to root DTAppend: Unable to find parent, null, for next-level-cache. Adding to root DTAppend: Unable to find parent, null, for cache-unified. Adding to root DTAppend: Unable to find parent, null, for arm,tag-latency. Adding to root DTAppend: Unable to find parent, null, for arm,data-latency. Adding to root DTAppend: Unable to find parent, null, for status. Adding to root DTAppend: Unable to find parent, null, for reset-names. Adding to root DTAppend: Unable to find parent, null, for resets. Adding to root DTAppend: Unable to find parent, null, for phy-mode. Adding to root DTAppend: Unable to find parent, null, for snps,phy-addr. Adding to root DTAppend: Unable to find parent, null, for phy-addr. Adding to root DTAppend: Unable to find parent, null, for txc-skew-ps. Adding to root DTAppend: Unable to find parent, null, for rxc-skew-ps. Adding to root DTAppend: Unable to find parent, null, for txen-skew-ps. Adding to root DTAppend: Unable to find parent, null, for rxdv-skew-ps. Adding to root DTAppend: Unable to find parent, null, for rxd0-skew-ps. Adding to root DTAppend: Unable to find parent, null, for rxd1-skew-ps. Adding to root DTAppend: Unable to find parent, null, for rxd2-skew-ps. Adding to root DTAppend: Unable to find parent, null, for rxd3-skew-ps. Adding to root DTAppend: Unable to find parent, null, for txd0-skew-ps. Adding to root DTAppend: Unable to find parent, null, for txd1-skew-ps. Adding to root DTAppend: Unable to find parent, null, for txd2-skew-ps. Adding to root DTAppend: Unable to find parent, null, for txd3-skew-ps. Adding to root DTAppend: Unable to find parent, null, for max-frame-size. Adding to root DTAppend: Unable to find parent, null, for altr,sysmgr-syscon. Adding to root DTAppend: Unable to find parent, null, for reset-names. Adding to root DTAppend: Unable to find parent, null, for resets. Adding to root DTAppend: Unable to find parent, null, for reset-names. Adding to root DTAppend: Unable to find parent, null, for #reset-cells. Adding to root DTAppend: Unable to find parent, null, for speed-mode. Adding to root DTAppend: Unable to find parent, null, for clock-frequency. Adding to root DTAppend: Unable to find parent, null, for i2c-sda-falling-time-ns. Adding to root DTAppend: Unable to find parent, null, for i2c-scl-falling-time-ns. Adding to root DTAppend: Unable to find parent, null, for lcd@0. Adding to root DTAppend: Unable to find parent, null, for sdmmc_clk_divided. Adding to root DTAppend: Unable to find parent, null, for clocks. Adding to root DTAppend: Unable to find parent, null, for #address-cells. Adding to root DTAppend: Unable to find parent, null, for #size-cells. Adding to root DTAppend: Unable to find parent, null, for broken-cd. Adding to root DTAppend: Unable to find parent, null, for cap-mmc-highspeed. Adding to root DTAppend: Unable to find parent, null, for cap-sd-highspeed. Adding to root DTAppend: Unable to find parent, null, for bus-width. Adding to root DTAppend: Unable to find parent, null, for device-width. Adding to root DTAppend: Unable to find parent, null, for bank-width. Adding to root DTAppend: Unable to find parent, null, for compatible. Adding to root DTAppend: Unable to find parent, null, for altr,dw-mshc-ciu-div. Adding to root DTAppend: Unable to find parent, null, for altr,dw-mshc-sdr-timing. Adding to root DTAppend: Unable to find parent, null, for supports-highspeed. Adding to root DTAppend: Unable to find parent, null, for slot@0. Adding to root DTAppend: Unable to find parent, null, for cd. Adding to root DTAppend: Unable to find parent, null, for cd-gpios. Adding to root DTAppend: Unable to find parent, null, for vmmc-supply. Adding to root DTAppend: Unable to find parent, null, for vqmmc-supply. Adding to root DTAppend: Unable to find parent, null, for #address-cells. Adding to root DTAppend: Unable to find parent, null, for #size-cells. Adding to root DTAppend: Unable to find parent, null, for master-ref-clk. Adding to root DTAppend: Unable to find parent, null, for ext-decoder. Adding to root DTAppend: Unable to find parent, null, for spidev@0. Adding to root DTAppend: Unable to find parent, null, for snps,nr-gpios. Adding to root DTAppend: Unable to find parent, null, for snps,nr-gpios. Adding to root DTAppend: Unable to find parent, null, for phys. Adding to root
Linux mSGDMA Driver Agilex 5
I am trying to use stream-to-memory DMA to move data. This is the design, showing the important Quartus connections: Which corresponds to this address config: # address map write_sdram = 0x00000000 read = NULL (has no meaning in streaming to MM mode) msgdma_csr = 0x22000040 msgdma_descriptor = 0x22000060 # msgdma offsets msgdma_csr_control = 0x4 + 0x22000040 = 0x22000044 msgdma_descriptor_write_low = 0x4 + 0x22000060 = 0x22000064 msgdma_descriptor_length = 0x8 + 0x22000060 = 0x22000068 msgdma_descriptor_control = 0xc + 0x22000060 = 0x2200006c The oscillator IP generates a group of known numbers, so the readbacks change each time - but are predictable and so the hardware is verifiable. In U-Boot; I have verified that this design. This script asks the DMA to make two transfers, and reads back the results each time. SOCFPGA_AGILEX5 # mw 0x22000044 0x1 # Stop Dispatcher SOCFPGA_AGILEX5 # mw 0x22000044 0x20 # Stop descriptors SOCFPGA_AGILEX5 # mw 0x22000044 0x2 # Reset Dispatcher SOCFPGA_AGILEX5 # mw 0x22000064 0x00000000 # Write address SOCFPGA_AGILEX5 # mw 0x22000068 0x8 # Write length in bytes SOCFPGA_AGILEX5 # md 0x22000040 1 # Check status 22000040: 00000002 .... SOCFPGA_AGILEX5 # mw 0x2200006c 0x02000000 # Wait for response SOCFPGA_AGILEX5 # sleep 1 SOCFPGA_AGILEX5 # mw 0x2200006c 0x82000000 # execute SOCFPGA_AGILEX5 # md 0x22000040 1 # Check status 22000040: 00000002 .... SOCFPGA_AGILEX5 # md 0x00000000 1 # read 00000000: 00000000 .... SOCFPGA_AGILEX5 # mw 0x22000044 0x2 # reset SOCFPGA_AGILEX5 # mw 0x2200006c 0x82000000 # execute SOCFPGA_AGILEX5 # md 0x00000000 1 # read 00000000: 67676767 .... When trying to do the same in linux using 'devmem2', I found that the readbacks did not change, so I decided to look for some examples. I found this stream-to-mapped mSGDMA driver built for the Cyclone V, and so re-purposed it. The driver example above both reads and writes to the device using the ‘dd’ utility in linux, but I am for now only interested in the read command. To do so I needed some information... Based on the .qsys design file output of my project, the mSGDMA block generates this interrupt: ... <altera:connection altera:kind="interrupt" altera:version="24.3" altera:start="subsys_hps.f2h_irq0_in" altera:end="msgdma_0.csr_irq"> <altera:connection_parameter altera:parameter_name="irqNumber" altera:parameter_value="2"> </altera:connection_parameter> </altera:connection> ... And according to the interrupt docs, the above csr interrupt value=2 maps to the GIC interrupt 51, which is 19 when referenced from the linux device tree. With this information, I have defined the following mSGDMA element in the .dts: ... msgdma_test: msgdma_test@22000000 { compatible = "msgdma_test"; reg = <0x0 0x22000000 0x0 0x100>; interrupt-parent = <&intc>; interrupts = <0 19 4>; }; ... Which only differs from the original in that it has a different interrupt number, and different base address - also accounting for the lwhps2fpga offset, due to it being the Agilex5 and not the Cyclone. The driver code from the REDS blog post has also been edited in the following way: I need to change a deprecated function in the main driver code: devm_ioremap_nocache to demv_ioremap. I want to see the data which has been moved - to do so have added an info print to the msgdma_read method: printk(KERN_INFO "MSGDMA: Read buffer content: %.*s\n", (int)read_ret, (char*)data->dma_buf_rd); There is only 1 interrupt, so we set data->msgdma1_irq = platform_get_irq(pdev, 0); Since there is no ability coded to fabric to perform msgdma_write - we can also remove memory allocations, remaps and references to msgdma0 and other write related objects. I think the following shows that the DMA is firing interrupts, and so I am confident that I have connected the correct interrupt: cat /proc/interrupts | grep msgdma 50: 2 0 0 0 GICv3 51 Level msgdma1 However, when looking at the kernel outputs after requesting reads via dd: $ dd if=/dev/msgdma_test of=/dev/null bs=8 count=1 $ dmesg | tail [ ... ] MSGDMA: Read buffer (hex): 00 00 00 00 00 00 00 00 [ ... ] MSGDMA: Read buffer (hex): 00 00 00 00 00 00 00 00 The driver code in question is included in msgdma.c and header_msgdma.c, attached to the post (This forum does not seem to like .h files...) I was hoping someone might have an idea of where I went wrong! Any helpers are much appreciated! Thanks for your time, K
Using Uart IP with HPS(Cyclone V soc dev board)
Hi I'm using HPS and want to use the UART IP to create a FPGA module to make a connection between the host and the board. Here is the system HPS : Buffer ====> | FPGA: Uart module ====> | TTL to RS232 module ====> | Host I've read the example of the RS232 Max Baurd rate example and the IP guide. I don't know if the HPS support this example for I DID NOT USE THE NOIS II. Instead I'm using the HPS with HWLIB. In HWLIB there is a 16550 uart API. Is that related to the RS232 IP? Is there an example for HPS? Is it allowed to reach the 921600 baud rate? thank you for your time Best Wishes Alex"DMA engine initialization failed" error when EMAC uses GMII interface
I am seeing the error given here when I boot the Agilex A5 (Quartus 24.3). This doc recommends to connect mac_tx_clk_i to a 2.5/25 MHz clock source 'correctly'. What does it mean, 'correctly'? There is a field in the HPS docs for this signal here, but this also does not specify what 'correctly' means. For further reference, I am trying to connect EMAC0 to EMAC1. Also here is the .dts: &gmac0 { status = "okay"; mac-mode = "gmii"; phy-mode = "gmii"; fixed-link { speed = <1000>; full-duplex; }; }; &gmac1 { status = "okay"; mac-mode = "gmii"; phy-mode = "gmii"; fixed-link { speed = <1000>; full-duplex; }; }; Many thanks! K
PMBUS Error During Configuration on Generated Example Design
Currently attempting to run the example Low Latency Ethernet 10G MAC on the Stratix 10 SX SoC H-Tile (1SV280HU2F50E1VGAS) devkit. I've generated the example design as stated in the Low Latency Ethernet 10G MAC Intel Stratix 10 FPGA IP Design Example User Guide. Working to try and load this design onto the above board but am running into an error shown on the image attached. This has been tested on two different H-Tile Stratix 10 devkits and the same issue occurs both times. I've attempted to load other designs which I've been told previously worked on these devkits and I am continually getting this error. This includes a previous iteration of the LL Ethernet 10G MAC design from a previous developer. I've spent some time looking at specific issues and off shoot solutions I've seen on Google but to no avail. Looking for some assistance pinning down what potentially is going on (whether its a board issue, a programmer issues, design issues, etc). Appreciate any assistance!
Main Features Released in 25.1.1
Main Features Released in 25.1.1: Initial support of the Agilex 3 device. Released GSRD for the Agilex 3 C-Series Development Kit. Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-3/c-series/gsrd/ug-gsrd-agx3/ DDR ECC support in the Agilex 5. Support of production Agilex 7 F-Series Crypto device. GSRD for DK-DEV-AGF0123FA dev kit (using production AGFD023R24C2E1VC ) replaces the DK-DEV-AGF027F1ES dev kit (using engineering sample AGFB027R24C2E2VR2). Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-7/f-series/fpga/gsrd/ug-gsrd-agx7f-fpga/ Support of USB 3.1 in Agilex 5 GSRDs. Support of booting from eMMC in ATF to Linux Direct boot for Agilex 5 device. Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/#boot-from-emmc_1 Removed generation of NAND binaries in Agilex 5 GSRD. Will be re-enabled when production devices get released.
Validating ECC Functionality on Custom Agilex 5 SOM in Linux Kernel
We are now looking to validate ECC (Error Correction Code) functionality on our custom Agilex 5 System-on-Module (SOM) running Linux. Our objective is to ensure that ECC is correctly enabled and functioning across all relevant memory regions, and that error detection and correction mechanisms are properly integrated at the kernel level. Could you please provide guidance on the necessary kernel configurations, device tree modifications, and available tools or procedures to test and monitor ECC behavior on this platform? Any documentation or reference designs specific to Agilex 5 ECC support would be highly valuable.
