Why USB-Blaster II does not work after closing the Quartus® Programmer Hardware Setup window?
Description When using Quartus® Prime Standard Edition to program a MAX® 10 FPGA device with a USB-Blaster II, changing the Hardware Setup frequency from the default 24 MHz to 16 MHz and then closing the Hardware Setup window with the Close button may cause the USB-Blaster II to stop functioning. Resolution Here are some practical solutions you can try to resolve the issue: 1. Restart the JTAG server. jtagserver --stop jtagserver --start 2. Unplug and replug the USB-Blaster II. 3. Kill lingering processes such as the JTAG server or Quartus Programmer process. jtagserver.exe quartus_pgm.exe 4. Change the clock frequency of the USB-Blaster II download cable to lower frequency like 16Mz and 6Mz. Related KDB: How do I change the clock frequency of the USB-Blaster II download cable? | Altera Community - 342304 5. Avoid USB conflicts by disconnecting other USB serial devices, especially FTDI or USB-UART adapters, and avoid opening COM ports or serial terminal applications while programming. 6. Try a different USB port and connect the USB-Blaster II directly to the PC instead of through a USB hub. 7. Reinstall the driver from the Quartus installation folder or try an older or known-stable driver version. 8. Avoid mixing drivers from multiple Quartus versions. 9. If a USB hub is required, avoid poor-quality or legacy USB 1.0 hubs. 10. If a clone USB-Blaster is being used, replace it with a known-good cable. 11. If none of the above steps recover the problem, reboot the system. Possible root causes: 1. JTAG server gets stuck and keeps the USB-Blaster II claimed. The device can appear normal in the operating system but remain inaccessible from Quartus Programmer. Restarting Quartus alone often does not recover the cable. Fix: jtagserver --stop jtagserver --start Or kill the process via Task Manager. 2. USB or driver conflicts with other devices. Conflicts with other devices, especially FTDI or USB-UART adapters, can break the USB-Blaster II mid-session. Opening a serial terminal can trigger the failure. This behavior is reported more often on Windows 64-bit systems. Fix: Disconnect other USB serial devices. Avoid opening COM ports or serial terminal applications while programming. Try a different USB port with a direct connection instead of a USB hub. 3. Driver bugs or Quartus version mismatches. Driver bugs or Quartus version mismatches can prevent Quartus Programmer from detecting the cable. Known bad driver versions or incompatible Quartus releases can cause the Programmer to lose the cable or prevent the standalone Programmer from detecting it. Fix: Reinstall the driver from the Quartus installation folder. Try an older or known-stable driver version. Avoid mixing drivers from multiple Quartus versions. 4. USB hub or signal quality problems. USB hub or signal quality problems can cause the USB-Blaster II to disappear after use. This is reported more often with poor-quality hubs or legacy USB 1.0 hubs. Fix: Plug the USB-Blaster II directly into the PC. Avoid poor-quality or legacy USB 1.0 hubs. 5. Clone USB-Blaster hardware. Clone USB-Blaster hardware can be unstable due to timing issues, firmware quirks, or driver incompatibilities. Fix: Replace the clone USB-Blaster with a known-good cable. 6. Closing Quartus Programmer leaves the cable in a bad state. Closing Quartus Programmer can leave the JTAG server running. It can leave the device handle locked. It can trigger USB re-enumeration issues on the USB stack. When Quartus Programmer is reopened, it may not be able to reattach to the already claimed cable. Fix: Unplug and replug the USB-Blaster II. Kill lingering JTAG server or Quartus Programmer processes. Reboot the system if the cable is still not detected.Why is the Avalon MM interface optimized away when using the SDI Audio Embed or SDI Audio Extract IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and earlier, the SDI Audio Embed IP and SDI Audio Extract IP might show incorrect behaviour when the generated IP name is audio_embed or audio_extract. In this condition, the affected output ports are left undriven and connected to the default value gnd, you will see messages similar to those shown below: Output port "reg_waitrequest" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u0" of entity "audio_extract" does not have a driver. Connecting to the default value "gnd". Output port "reg_waitrequest" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdatavalid" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Output port "reg_readdata[0..7]" in instance "u1" of entity "audio_embed" does not have a driver. Connecting to the default value "gnd". Resolution To work around this problem, use a different IP name to avoid a naming that conflicts with the generated HDL module naming used by the Quartus® Prime Pro Software for the SDI Audio Embed or SDI Audio Extract IP. For example: Do not name the SDI Audio Embed IP as audio_embed. Do not name the SDI Audio Extract IP as audio_extract. Regenerate the IP after renaming it to a non-conflicting name. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why do I get Error (169059) when compiling for MAX® 10 FPGA (Dual Supply) B610 package with 1.0 V I/O standard?
Description In Quartus® Prime Standard Edition 25.1 and earlier, compiling a design targeting MAX® 10 dual power supply devices of the B610 package fails when the design uses a 1.0 V I/O standard assignment. Observed error: Error (169059) The MAX® 10 FPGA General Purpose I/O User Guide indicates that the 1.0 V LVCMOS I/O standard is available only for specific device combinations, and the dual power supply devices of the B610 package are part of that. Resolution This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why does Board Support Package Editor fail to generate embedded peripheral IP drivers when generating BSP FreeRTOS project for Nios® V processor?
Description Due to a problem in the Quartus ® Prime Standard Edition Software version 24.1 and 25.1, the BSP Editor fails to generate embedded peripheral IP drivers, when it is generating BSP FreeRTOS project for Nios ® V processor. This is because the BSP Editor is not enabled to generate those drivers in FreeRTOS. Refer to Embedded Peripherals IP User Guide - Driver Support for the list of embedded peripherals with driver support. Resolution Patches are available to fix this problem for the Quartus ® Prime Standard Edition Software version 24.1 and 25.1 Linux and Windows versions. Download and install patch below. Quartus® Prime Standard Edition Software v24.1 Patch 0.01 Quartus® Prime Standard Edition Software v25.1 Patch 0.01 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition Software.What should I consider when designing a system board using Schmitt trigger inputs on MAX® 10 FPGAs?
Description When designing a system board that uses Schmitt trigger inputs on MAX® 10 FPGAs, board-level noise, power integrity, and signal integrity can significantly affect the effective hysteresis behavior. Factors such as power supply noise, input signal noise, and PCB layout practices may cause the observed switching thresholds to deviate from their typical values. This article outlines key considerations to help minimize noise sensitivity when using Schmitt trigger inputs in a system-level design Resolution When designing a system board that uses Schmitt trigger inputs, consider the following: Follow the recommendations in the MAX® 10 FPGA Design Guidelines, especially sections related to power distribution network (PDN) and signal integrity. Minimize power supply noise by using proper decoupling, grounding, and PCB layout practices. Note: The MAX® 10 FPGA 10M08 Evaluation Kit is intended for low-cost application testing and is not designed for DC or PDN characterization. It should not be used to measure intrinsic transistor switching thresholds.Why are some simulation library files missing when compiling for Questasim*?
Description Due to a problem in Simulation Library Compiler in the Quartus® Prime Standard Edition Software 23.1 and later, you may see some Quartus® Simulation Library source files not included for compilation for Siemens* Questasim* Tool selection. This problem persists on both EDA Simulation Library Compiler GUI and command line versions. This problem only exists in Quartus® Prime Standard Edition and does not affect Quartus® Prime Pro Edition versions. Resolution To work around this problem, follow these steps: 1. Edit file: <QUARTUS INSTALLATION DIRECTORY>/quartus/common/tcl/internal/simlib_comp.tcl 2. Replace: set gl(primary_tool,questasim) questasim With: set gl(primary_tool,questasim) modelsim This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why does the outclk of the ALTCLKCTRL IP remain enabled when using the ENA input in External Path mode?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 or earlier, you might see that the output clock of the ALTCLKCTRL IP remains enabled regardless of whether the ENA input is asserted or de‑asserted when using the “External path” mode. This problem occurs because the ENA input port is not used in “External path” mode even if the “Create ‘ena’ port to enable or disable the clock network driven by this buffer” option is selected. Beginning with the Quartus® Prime Standard Edition Software version 23.1, the software will generate an error message indicating that the “Create ‘ena’ port” option is unavailable when the “External path” type is selected. Resolution To work around this problem using the ALTCLKCTRL IP with the “External path” mode: Disable the “Create ‘ena’ port to enable or disable the clock network driven by this buffer” option in the Parameter Editor. If you require clock gating, implement the gating logic external to ALTCLKCTRL (for example, gate the source clock or use an alternate supported clock‑control scheme) rather than relying on the ALTCLKCTRL ENA port in “External path” mode.Error: $MODEL_TECH/../intel/verilog/src/mentor/twentynm_atoms_ncrypt.v(38): in protected region
Description Due to a problem in the Quartus® Prime Standard Edition Software, you might see this error message when simulating the ASMI (Active Serial Memory Interface) Parallel IP for Arria® 10 FPGA devices. This is due to the simulation libraries for the ASMI Parallel IP is missing in the Quartus® Prime Standard Edition Software. Resolution To work around this problem, upgrade the design to the Quartus® Prime Pro Edition Software. The simulation libraries for the ASMI Parallel IP are available in the Quartus® Prime Pro Edition Software. This problem is not scheduled to be fixed in the Quartus® Prime Standard Edition Software. Related IP Core ASMI Parallel IPWhy does niosv-download return “Invalid reset option” when executing reset from debug module?
Description Due to a problem in the Ashling RiscFree IDE for Altera® software, the niosv-download returns “Invalid reset option” when executing reset from debug module for designs targeting Nios ® V processor. The affected versions are: Software version 25.2.1 (version dated 9 th May 2025, paired with Quartus® Prime Pro software version 25.1.1 and Quartus® Prime Standard software version 25.1) Software version 25.3.1 (version dated 1 st Aug 2025, paired with Quartus® Prime Pro software version 25.3.1) Software version 25.4.1 (version dated 31 st Oct 2025, paired with Quartus® Prime Pro software version 26.1) The problem is caused by Ashling GDBServer failing to execute software reset (swreset), and niosv-download is using Ashling GDBServer to communicate with the processor. Thus, this failure prompts the “Invalid reset option” message when executing “niosv-download –r". Resolution To work around this problem, use the argument “-o” to change from Ashling GDBserver to OpenOCD. $ niosv-download –r -o This problem is fixed beginning with the Ashling RiscFree IDE for Altera® Quartus® software version 26.1.1-C, which is paired with Quartus® Prime Pro software version 26.1.1. Related Articles NIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10) | Altera Community - 352387Why does Quartus® Prime Standard Edition Software v24.1 hang and fail to close after using the Programmer?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 and later, the Quartus® Prime Standard Edition Software might become unresponsive and fail to close after running the Quartus® Prime Programmer on Windows* 10 environments. The typical sequence that triggers the hang is: Launch the Quartus® Prime Standard Edition Software. Launch the Quartus® Prime Programmer from within the Quartus® Prime Standard Edition Software and complete programming. Close the Quartus® Prime Programmer. Attempt to close the Quartus® Prime Standard Edition Software. Result: Windows shows “Not Responding” and the application must be forcibly terminated. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 24.1, download and install the patch below: This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.