Agilex® 7 M-Series Expands with Three New Package Options for Increasing Bandwidth and Connectivity
Altera introduced three new Agilex® 7 M-Series FPGA package options, R31G, R47C, and R47D, to give customers more flexibility in balancing bandwidth, connectivity, and performance for AI, networking, video, embedded, and acceleration applications. The new options support DDR5-6400, up to 204.8 GB/s memory bandwidth, and expanded transceiver configurations, enabling designers to optimize systems for PCIe connectivity, maximum data throughput, or efficient right-sized scaling.Agilex® 7 F-Tile at 200G: High-Speed Ethernet in Action
This post demonstrates a 200G-4 Ethernet link running on Agilex 7 FPGAs using F-Tile transceivers. It walks through the full link bring-up process, including Auto-Negotiation and Link Training, followed by stable high-speed data transmission using 53.125G PAM4 lanes over QSFP-DD. The demo provides real-time visibility into link status, signal integrity, and error metrics, and evaluates performance across loopback configurations and varying cable lengths. The result highlights reliable link initialization, consistent throughput, and robust operation under practical system conditions.Beyond Traditional Mid-Range: The Agilex® 5 Approach
This post explains how the definition of mid-range FPGAs has evolved from logic density to system-level capability. It highlights how Agilex 5 FPGAs address modern embedded and edge requirements by integrating compute, AI acceleration, memory, connectivity, and security into a single platform. The article also covers how Agilex 5 D-Series extends mid-range performance with higher logic density, increased bandwidth, and enhanced AI capabilities, enabling more complex and data-intensive workloads while maintaining efficiency and design simplicity.Enabling Runtime Flexibility in High-Speed Designs with F-Tile Dynamic Reconfiguration
This post demonstrates how F-Tile Dynamic Reconfiguration in Agilex 7 FPGAs enables real-time switching between 400G and 4×100G Ethernet without system downtime. It explains how predefined configuration profiles, system-level data path reconfiguration (MAC, PCS, FEC, PMA), and software control enable predictable, production-ready transitions. The article also highlights support for multi-rate Ethernet, protocol flexibility, and continuous traffic validation, showing how FPGA-based systems can adapt dynamically to changing network conditions.From Talk to Deployment: Altera at Mobile World Congress 2026
This blog recaps Altera’s presence at Mobile World Congress 2026, highlighting a shift in the wireless industry from experimentation to real-world deployment. It covers key announcements such as validated interoperability with Broadcom for 5G-Advanced and early 6G radio systems, production-ready massive MIMO reference designs, and growing momentum in satellite (NTN) communications. The post also showcases FPGA-based AI use cases running directly at the RAN edge and emphasizes the strength of Altera’s partner ecosystem. Overall, it presents practical advancements in scalable, power-efficient wireless infrastructure built on Agilex FPGAs.Altera Extends Agilex®, MAX® 10, and Cyclone® V Lifecycles Through 2045 for Long-Life Systems
Altera is extending the availability of its Agilex®, MAX® 10, and Cyclone® V FPGA families through 2045 to support long-lifecycle applications like industrial, aerospace, and medical systems. This helps customers avoid costly redesigns and ensures reliable, long-term supply, reinforcing Altera as a trusted partner for decades-long deployments.
How Agilex® FPGAs Extend Infrastructure Lifecycles by Replacing End-of-Life ASSPs
Modern infrastructure systems are facing growing challenges as many legacy ASSPs and ASIC devices reach end-of-life, creating pressure to find scalable and future-ready alternatives. FPGAs are emerging as a powerful replacement platform, offering programmability, lifecycle extension, and adaptability to evolving standards such as DDR5 and post-quantum security. With platforms like Altera’s Agilex family, organizations can replace fixed-function silicon while maintaining high performance, flexibility, and long-term production viability.Pushing FPGA Fabric Performance Toward 1 GHz with Agilex® 7
Agilex® 7 FPGAs push FPGA fabric performance toward the gigahertz range by combining the HyperFlex® architecture with Quartus® Prime Pro software optimization. In Altera testing, a 32-bit SIMT soft processor implemented on Agilex 7 operated above 950 MHz, demonstrating how high-performance soft logic can be achieved in real designs. Hyper-registers distributed throughout the routing fabric enable deeper pipelining and advanced retiming, while Quartus Prime Pro optimizes synthesis, placement, routing, and timing to reach aggressive clock targets—allowing compute-intensive FPGA workloads to run faster and scale more efficiently.Agilex® 7 FPGAs Demonstrate Linear Pluggable Optics (LPO) for AI and Cloud Infrastructure
Linear Pluggable Optics (LPO) is gaining traction for AI/cloud infrastructure because it removes DSPs from optical modules, shifting signal conditioning to the host—cutting power by 30–40%, simplifying design, and lowering latency. Altera demonstrated public LPO interoperability using Agilex™ 7 devices running 400GbE (4×100G) with performance well beyond LPO spec thresholds in lab testing. Agilex 7’s high-speed transceivers and integrated capabilities make it a strong fit for SmartNICs, DPUs, and AI offload, with a roadmap toward next-gen 200G/224G LPO standards.The Agilex DDR5 Advantage: Future-Proof Memory Leadership Starts Today
As the industry accelerates its transition from DDR4 to DDR5 and LPDDR5, memory choices are becoming a defining factor in system longevity, performance, and supply continuity. Altera is uniquely positioned to help customers navigate this shift with production-ready DDR5 and LPDDR5 solutions available today across a broad FPGA portfolio. DDR5 Is the New Standard Major memory vendors have announced plans for DDR4 end-of-life plans or significant production reductions, with full transitions to DDR5, LPDDR5, and next-generation memory already underway. While DDR4 will remain available for long lifecycle segments through multiple suppliers, new design starts today are increasingly looking to DDR5 and LPDDR5. Altera’s Head Start in DDR5 and LPDDR5 While DDR5 and LPDDR5 support is emerging across the industry, Altera stands apart with the broadest set of production devices supporting these standards across high-performance, mid-range, and power-optimized platforms: Agilex™ 7 M-Series and Agilex™ 5 devices support DDR5 and LPDDR5 for high-performance and embedded applications Altera is also planning to add LPDDR5 support within Agilex™ 3 devices, reinforcing its long-term design scalability. Competitive Advantage Across Every Market Tier Altera’s memory leadership spans across a range of design requirements: - High-Performance designs: Agilex™ 7 AGM032 and AGM039 support: DDR5 up to 5,600 MT/s LPDDR5 up to 5,500 MT/s - Mid-Range designs: Agilex™ 5 D-Series support: DDR5 up to 5,600 MT/s LPDDR5 up to 5,500 MT/s - Power/Cost-optimized designs: Agilex™ 3 support: LPDDR5 up to 2133 MT/s Unlike FPGA-only devices, Agilex integrates an optional HPS that allows DDR5 and LPDDR5 to function as a shared memory resource for both processing and acceleration, delivering higher effective bandwidth and system efficiency. Key Takeaway With DDR5 and LPDDR5 moving from ‘next-generation’ to ‘now,’ Altera offers customers a clear advantage: production-ready memory leadership, a broad and scalable FPGA portfolio, and a smooth transition path from DDR4 to DDR5—without waiting for future silicon. Download the The Agilex™ 5 SoC Memory Advantage with DDR5 and LPDDR5 White Paper
