Agilex™ 3 FPGAs and SoCs Deliver Up to 62% Faster Core Performance than Competing FPGAs

In cost-optimized applications, engineers constantly balance power, performance, and logic utilization. With the Altera Agilex™ 3 FPGA family, developers can achieve high-performance compute without compromising size, cost, or efficiency.

We recently benchmarked ten open source and OpenCores designs across both Agilex 3 and Lattice Certus-N2 devices. The results speak for themselves:

• Up to 62% higher fabric fmax performance and

• 29% higher geometric mean for Agilex 3 vs. Certus-N2

To deliver a transparent, reproducible comparison, we selected the designs spanning a wide range of applications: signal and image processing, cryptographic blocks (AES, MD5, RC4), error correction (Reed-Solomon), RISC-V and general-purpose processors (PicoRV32, M1), and arithmetic and floating-point units. Each design was compiled with high-effort timing constraints using the latest versions of vendor-recommended tools:

• Altera Quartus® Prime 25.1 (Agilex 3 device)

• Lattice Radiant 2024.2 (Certus-N2 device)

To reflect representative system-level workloads, we employed a stamping methodology that instantiated multiple copies of each design in parallel across the device. This subjected the FPGA fabric of each device to high resource utilization and increased routing complexity, conditions commonly encountered in real designs.

Results and Key Findings from System-Level Benchmarking Using Parallel Design Stamping

In nine out of ten designs, the slowest Agilex 3 device matched or exceeded the fastest Certus-N2 device, equivalent to a one-to-two speed grade advantage in real terms.

What This Means for FPGA Developers:

The performance benefits seen in Agilex 3 devices are the result of several innovations. At the core is Altera’s 2nd Generation HyperFlex™ architecture, which enables higher timing margins through deeper pipelining and register retiming. Combined with an efficient routing fabric and a powerful and easy-to-use toolchain, Agilex 3 devices are optimized for closing timing even in high-utilization scenarios prone to routing congestion.

For developers building:

• Embedded compute systems

• Edge AI accelerators

• Signal processing or cryptographic engines

• Projects using open-source RTL

The Agilex 3 family delivers exceptional performance-per-area, without requiring migrating to more expensive, higher-density, or higher-speed devices. That means lower cost and faster time-to-market.

Get the Whitepaper

The full benchmark methodology, stamping methodology, RTL sources, and Fmax plots are detailed in our free whitepaper:
Agilex 3 vs Certus-N2 Whitepaper