Why are Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach missing from Quartus® Prime Pro software IP Catalog?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1 and 26.1, Vectored Interrupt Controller IP and Trace Interface IP for Lauterbach are missing from IP Catalog. It is due to a bug in the IP Catalog. Refer to Embedded Peripherals IP User Guide - Device Support (PDF) for the Vectored Interrupt Controller IP device support. Refer to Nios® II – Lauterbach Trace32 Debug system for more information about Trace Interface IP for Lauterbach. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 26.1. Download and install patch 0.11 below. Quartus® Prime Pro Edition Software v26.1 Patch 0.11 This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Pro Edition Software.Why does Board Support Package (BSP) Editor in Quartus® Prime Pro Embedded Edition fails to generate Nios® V processor BSP project from .vds file?
Description Due to a problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, the BSP Editor fails to generate Nios® V processor BSP project from .vds file. This issue is not affecting BSP project generation: From .qsys file using BSP Editor in Quartus® Prime Pro Embedded Edition software, or Using BSP Editor in Quartus® Prime Pro Edition software. This issue is caused by a software bug in the BSP Editor of Quartus® Prime Pro Embedded Edition software. Refer to Nios V Embedded Processor Design Handbook - Recommended Tools from Quartus Prime Installer (PDF) for more information on the difference between Quartus® Prime Pro Edition and Quartus® Prime Pro Embedded Edition software. Resolution To work around this problem in the Quartus® Prime Pro Embedded Edition Software version 26.1 and 26.1.1, apply either one of the workarounds below: Switch from .vds to .qsys file Use BSP Editor in Quartus® Prime Pro Edition software version 26.1 or 26.1.1 This problem is currently scheduled to be resolved in a future release of the Quartus® Prime Pro Embedded Edition Software.Why does the quartus_pfg tool hang when generating an encrypted bitstream file?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, the quartus_pfg tool may hang indefinitely while generating an encrypted bitstream file. This is an intermittent problem. Once it occurs for a specific FPGA bitstream, it will always occur for that bitstream. Resolution A patch is available to fix this problem for the Quartus ® Prime Pro Edition Software version 25.3.1. Download and install patch 1.18 This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Can I automatically legalize memory IPs with conflicting locations in Power and Thermal Analyzer?
Description When you add multiple memory interface IPs to a PTA design, they do not get automatically allocated into multiple IO banks. This can cause errors from having too many interfaces in a single IO bank. Resolution You may need to manually change location information for multiple interfaces to resolve the errors. Alternately, you can use a script to automate the process of allocating memory interfaces into multiple IO banks. To use the script, download it from this KDB and save it on your computer. Then run the following command in the Tcl console of PTA: source <path to file>/reallocate_emif_pins.tcl Additional Information The script uses a simple method to allocate memory interfaces into multiple IO banks. It does not perform a full legalization such as is performed by the Quartus® Prime Pro Edition software. Therefore, in certain limited cases, it may not be possible for the Quartus Prime Pro compiler to implement some memory interfaces in the locations generated by the script. Additionally, the script cannot resolve errors caused by having more memory interface IPs than are supported by the device. If you have too many memory interface IPs in your PTA design, you must remove some./quartus/pgm/bitasm/bitasm_bitstream_encryption.cpp, Line: 1439 Expected the extra routing value(8) to be 0 or 4.
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3, this error message might be displayed when generating an encrypted FPGA bitstream file using the quartus_pgm tool. This problem only affects some FPGA bitstream files. Resolution This problem is fixed beginning with version 26.1 of the Quartus® Prime Pro Edition Software.Why does "Display in New Tab" fail in the RTL Analyzer?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1 and earlier, you might see that "Display in New Tab" does not work for components in a design partition. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 25.3.1, download and install patch 1.27. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why can't the Altera FPGA IP Evaluation Mode be disabled?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might encounter the problem above where the warning message below does not appear even though the Altera® FPGA IP Evaluation Mode has been disabled. Warning Message: "Warning(23202): Intel FPGA IP Evaluation Mode feature is not used – it has been explicitly disabled for this design" Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 26.1.What is the latest device firmware for the Quartus® Prime Pro Edition Software version 25.1.1?
Description The latest device firmware for the Quartus® Prime Pro Edition Software version 25.1.1 can be downloaded from the following links. Fixes for the following problems are included in the latest release (The newest release contains all prior fixes and supersedes earlier device firmware releases). Change Log Firmware version 1.33fw: Fixed race condition in handling SHA isr and resumption of FPGA data blocks.Drain DMA post a configuration/PR to flush out left over data if any. Firmware version 1.22fw: Enabled 85 Ohm Rx Termination for PCIe designs. Resolved problem related to Ethernet Auto-Negotiation and Link Training (AN/LT) designs on F-Tile FGT having link up issue Resolved problem related to IEEE 802.3-2022 50GBASE-KR compliance testing marginality during Link Training (LT). Resolved problem related to FGT transceivers using certain FGT Attribute Access method sequence hanging. Firmware version 1.15fw: Added Safe SEU error injection mailbox command. Please also see the following links: Updating the SDM Firmware in the Agilex® FPGA Configuration User Guide Updating the SDM Firmware in the Stratix® 10 FPGA Configuration User Guide Resolution Download the latest device firmware below. Note: Patches must be applied to the Quartus® Prime Pro Edition Software and the Quartus® Prime Pro Edition Software Programmer and Tools. Recompilation is not required. All programming files should be recreated. Re-run the programming file generation or conversion using the Quartus® Prime Software programming file generator.Why do I see permission denied error in Windows (64-bit) when using ModelSim*- Altera® FPGA to simulate Agilex® 7 CPRI PHY IP Example Design on the Quartus® Prime Pro Edition software version 21.4?
Description The issue occurs when using ModelSim®–Altera FPGA to simulate the Agilex® 7 CPRI PHY IP Example Design on a Windows (64-bit) system. This problem does not occur when running the same simulation on a Linux system. Resolution To work around this problem: Create a new folder called temp under example testbench. Copy the MIF file into it. In the script ./example_testbench/sim_script/common/modelsim_files.tcl, revise the MIF path. lappend memory_files "[normalize_path "$QSYS_SIMDIR/../temp/cpriphy_ftile_hw__tiles__z1577a_x388_y0_n0.mif"]" Alternative: In the script ./example_testbench/sim_script/mentor/msim_setup.tcl, revise as follow. Line 188: file copy -force $file ./ ----> catch { file copy -force $file ./ } This problem is fixed beginning with the Quartus® Prime Pro Edition software version 22.2.Why do I see a simulation failure with the F-Tile Multi Channel DMA IP for PCI Express* Design Example using the Quartus® Prime Pro Edition Software version 26.1?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 26.1, you may encounter simulation errors with the F-Tile Multi Channel DMA IP for PCI Express* Design Example. Synopsys VCS/VCS-MX : Error-[SE] Syntax error Following verilog source has syntax error : "./../..//pcie_ed_sim_tb.v", 2015: token is ')'... Error-[TMENF-IL] Top Module/Entity not found Top module/entity/config "pcie_ed_sim_tb.pcie_ed_sim_tb" is not found in library "PCIE_ED_SIM_TB". Error-[NM] No modules defined No modules defined in current design file(s). Siemens QuestaSim: ** Error: /mentor/questasim/2025.3/linux64/linux_x86_64/qrun failed. Error in macro ./run_msim_setup.tcl line 52 Cadence Xcelium: xmelab: *E,NOUNIT: Unable to find a unit named 'pcie_ed_sim_tb.pcie_ed_sim_tb' in the libraries. xmsim: *F,NOSNAP: Snapshot 'pcie_ed_sim_tb.pcie_ed_sim_tb' does not exist in the libraries. Aldec Riviera-Pro: Error: VCP2000 .../pcie_ed_sim_tb/pcie_ed_sim_tb/sim/pcie_ed_sim_tb.v : (1951, 6): Syntax error. Unexpected token: ). This problem is attributed to a limitation in the provided simulation testbench within this software release. It is important to note that this behavior is confined to the simulation environment and does not impact the functionality or performance of the design on hardware. Resolution This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.
