Fatal Error: Read data comes back but dynamic OCT ctrl is not in read mode
Description You may see the following error when you simulate the UniPHY based DDR3 controller in full calibration mode. # ** Fatal: Read data comes back but dynamic OCT ctrl is not in read mode Resolution Open the following file in your simulation file-set: altdq_dqs2_ddio_3reg_<user_device>.sv Find the following line: (1, "Read data comes back but dynamic OCT ctrl is not in read mode"); Replace the line above with the following line: ("Read data comes back but dynamic OCT ctrl is not in read mode at time %f", ); The simulation should run without any errors once the above change is implemented.Why do I get a Fatal Error in Assembler when having ALTLVDS TX with a design?
Description You may see this error in the Quartus® Prime Software Standard version 17.0 or earlier. This error is due to either LVDS data output port “tx_out[*]” or external clock port “tx_outclock” of ALTLVDS TX IP is not assigned to LVDS I/O standard. Resolution To work around this problem, you should assign both the data output port and external clock output to the LVDS I/O standard.Is there a known issue with the Triple Speed Ethernet (TSE) LVDS Receive (Rx) and Transmit (Tx) general purpose PLLs merging in Quartus II software version 10.1?
Description Yes, the Triple Speed Ethernet IP has enhanced the LVDS Rx PLL reset sequence in Quartus® II software version 10.1. The LVDS Rx PLL now has pll_areset controlled via the tse_lvds_reset_sequencer, whilst the Tx PLL has its pll_areset tied inactive. As the input sources to the two PLLs are now different, Quartus II is no longer able to merge the two PLLs. This issue will be address in a future version of the IP.Error: The specified Memory clock frequency exceeds the Memory device speed grade of 533.333 MHz. Please increase the Memory device speed grade (in Memory Parameters tab) or decrease the Memory clock frequency.
Description You may see the above error when generating a Stratix IV DDR3 UniPHY controller in the Quartus® II software version 13.1 or later. There is a new frequency check in the MegaWizard™ Plug-in Manager IP GUI that prevents users from running the interface faster than the maximum supported frequency. If you specify the maximum supported frequency with more than 3 decimal places (i.e. 533.3333MHz), it will lead to the above error. Resolution The workaround is to limit the DDR3 Memory clock frequency in the PHY Settings tab of the MegaWizard™ Plug-In Manager to three decimal places.Is the hard transceiver 8B/10B encoder/decoder in Stratix, Arria, and Cyclone family transceiver devices Fibre Channel compliant?
Description No, the 8B/10B encoder/decoder does not satisfy all the requirements for the Fibre Channel protocol in Stratix® GX, Stratix II GX, Stratix IV GX/T, Arria® GX, Arria II GX, or Cyclone® IV GX devices. 1) Fibre Channel protocol requirements for 1.062 and 2.125 Gbps states that the transmitter needs to start up with negative running disparity. Further, the standard has disparity rules for Ordered Sets. -The embedded 8B/10B encoder does start up with negative disparity. However, the encoder does not contain the functionality to force negative current running disparity at any time. This is required to be able to meet the disparity rules for Ordered Sets. 2) Fibre Channel protocol requirements for "Detection of Invalid transmission Word" for 1.062 and 2.125 Gbps state that Ordered Sets received with incorrect beginning running disparity be flagged as an error. -The current 8B/10B implementation determines running disparity on a character-by-character basis and not Ordered Sets. Due to these non-compliances, customers may or may not be able to use the embedded 8B/10B encoder/decoder in the transceiver megafunction. This decision would have to be based on how the customer is implementing their Fibre Channel or Fibre Channel-like architecture. Possible workarounds: User would have to implement 8B/10B encoding and decoding blocks in the PLD core to be able to meet the specific requirements in both the transmit and receive directions. User could use 8B10B Encoder/Decoder MegaCore Function from Altera Corporation User could use Multi-Gigabit Fibre Channel Transport Core from MorethanIP References: Fibre Channel, Physical Signaling Interface (FC-PH) REV 2.13 December 4, 1991 Fibre Channel Framing and Signaling (FC-FS) REV 1.90Is it possible to retain data in a memory device during the UniPHY calibration process?
Description No, it is not recommended to rely on data being preserved in memory during UniPHY calibration as no refresh commands are issued to the external memory devices during calibration. Only the locations with calibration data patterns get refreshed by accesses to these locations. If you need to find out the actual address locations used in the UniPHY calibration, the recommended approach is to simulate the UniPHY IP example design for your memory IP configuration with the full calibration option. For further details refer to the External Memory Interface handbook, Chapters : Implementing and Parameterizing Memory IP (PDF) Simulating Memory IP (PDF) Functional Description - UniPHY (PDF)Are there any issues with the UniPHY IP Global Signal assignments seen in the Quartus II software Assignments editor after running the <variation_name>_pin_assignments.tcl script?
Description These assignments which are applied to UniPHY based IP's reset and clock signals are correct and no changes are required by the user. The assignments are shown with Status “?”. This is due to a display issue in Assignments editor and is planned to be fixed in a future version of the Quartus® II software.During simulation of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function, l8_rx_fcs_error goes to 'X' when l8_rx_fcs_valid is '1'
Description Due to a problem in the 40- and 100-Gbps Ethernet MAC and PHY MegaCore® Function, l8_rx_fcs_error may go to “X” when l8_rx_fcs_valid goes to '1'. Resolution To work around this problem, upgrade to the Quartus® II software version 13.1.Why does the Intel® PCIe* Hard IP run into recursive replay timer timeout, replay num rollover and link recovery when sending traffic?
Description You might see timeout, rollover, and recovery because of Start of Packet(SOP) pointer buffer overflow. The SOP pointer buffer can overflow during replay because of internal error message or TLPs submitted from user side for transmission when the following trigger conditions are met: - ACK packets are lost or not received by Intel® PCIe* Hard IP under a high bit error rate link conditions - Link partner is unable to ACK packets at regular intervals as per the spec for unknown reasons If the above trigger conditions persists, then there are chances that internal SOP pointer buffer will reach the full condition. Every replay after this will cause overflow because of error message scheduling (Replay Timeout, Replay Num Rollover) or TLPs are submitted from user side for transmission. Resolution There is no workaround to this problem. This problem will not be fixed in a future release of the Intel® Quartus® Prime software.Why cant I use a transceiver recovered clock to feed a transmitter PLL reference clock on Altera transceiver devices?
Description The Quartus® II Software will deliberately prevent you from connecting a recovered clock from a receiver to the reference clock input of a transmitter PLL. The recovered clock is extracted from the clock embedded in the received datastream. As the datastream has propagated across a channel, the recovered clock will have undefined jitter characteristics which if fed into the reference clock of a transmitter PLL, may cause the transmit jitter to exceed a given protocols' transmit jitter specification. The recommended method of implementing a recovered clock synchronous architecture is to route the recovered clock outside of the FPGA, and to pass the clock through a jitter cleaner before routing back onto the FPGA through one of the dedicated transceiver reference clock pins.