Why do I get a Fatal Error in Assembler when having ALTLVDS TX with a design?

Description

You may see this error in the Quartus® Prime Software Standard version 17.0 or earlier. This error is due to either LVDS data output port “tx_out[*]” or external clock port “tx_outclock” of ALTLVDS TX IP is not assigned to LVDS I/O standard.

Resolution

To work around this problem, you should assign both the data output port and external clock output to the LVDS I/O standard.