How to reduce ROM/RAM requirements for a NIOSV Compact CPU Platform?
Hello ALTERA NIOSV Experts, I am trying to create a system in Quartus Platform Designer which has the following components: A 1G Tri mode ethernet IP (with 32 bit AVALON-ST TX/RX interfaces using minimum sized FIFOs) A RS 232 UART with no FIFO A couple of small FIFOs using AVALON-ST interfaces for data in and out of Platform via Conduits A NIOSV Compact CPU A JTAG UART ROM for NIOSV RAM for NIOSV My questions are about how to reduce the ROM (for the NIOSV compacts program) and RAM to the minimum amount. I am trying to shoehorn this all into a MAX10 FPGA ( Altera Max 10 part number 10M08SAU169I7G). When i build the BSP for this platform, with a "Hello World" program, it seems to need around 128 Bytes of ROM and several KBytes of RAM. Why is the program so large ? I expect it has to do with the BSP adding in drivers for all the Platform IP and it is getting bloated. What tactics are available for me to use in the Ashling RISC FREE IDE which i am using to create my BSP and/or Platform Designer to reduce the program size ? The FPGA i am trying to use only has around 48 K Bytes of RAM available in total ...so maybe this is not possible and i need a bigger FPGA of course ! Thanks for your help, Dr Barry
NIOSV/g with FPU: inconsistent calculation results
I'm using a NIOSV/g with FPU enabled in a MAX10 project. The project involves heavy use of float point calculations, hence the need for the FPU. I noticed some occasionally inconsistent results in this program and started debugging - assuming this was a bug in my code. However I was able to run my code in a simulator and on a different RISCV microcontroller and everything worked flawlessly. I also disabled the FPU in the NIOSV design and again the code ran fine. In order to recreate the problem, I created a basic project with just the NIOSV, some RAM and the JTAG-Uart. I also wrote a tiny C program to stress test the FPU. The results of this show that again, the FPU is producing incorrect results. I've attached a screenshot of the Platform Designer design. I'm running the design at 75Mhz and the design meets timing requirements. Here is the code I ran. Note that I have interrupts disabled to be sure this isn't a context switching issue. I also did not wrap the calculations into a function so I could more easily view the various calculation results in the debugger. This code works as expected when using a soft-FPU. When using the NIOSV FPU, results are inconsistent. I've attached a screenshot of one failed cycled. You can see that a1 and b1 are not equal. #include <stdint.h> #include <math.h> #include "sys/alt_stdio.h" static void fpuTest(void) { int fail_count = 0; int iteration = 0; while (1) { float a0 = (float)iteration * 0.001f; float a1 = 1.1f * sinf((float)iteration * 0.1f); float a2 = 2.2f / (1.0f + (float)iteration * 0.0001f); float a3 = sqrtf(3.3f + (float)iteration); float a4 = powf(4.4f + (float)iteration, 1.1f); float a5 = logf(5.5f + (float)iteration + 1.0f); float a6 = 6.6f * cosf((float)iteration * 0.05f); float a7 = 7.7f + tanf((float)iteration * 0.02f); float result_a = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7; float b0 = (float)iteration * 0.001f; float b1 = 1.1f * sinf((float)iteration * 0.1f); float b2 = 2.2f / (1.0f + (float)iteration * 0.0001f); float b3 = sqrtf(3.3f + (float)iteration); float b4 = powf(4.4f + (float)iteration, 1.1f); float b5 = logf(5.5f + (float)iteration + 1.0f); float b6 = 6.6f * cosf((float)iteration * 0.05f); float b7 = 7.7f + tanf((float)iteration * 0.02f); float result_b = b0 + b1 + b2 + b3 + b4 + b5 + b6 + b7; // Check if result is consistent (should be identical) if (fabsf(result_a - result_b) > 1e-6f) { alt_printf("FPU test failed at iteration %x\n", iteration); fail_count++; } iteration++; } } int main(void) { // Make sure interrupts are disabled __asm volatile ( "csrc mstatus, 8" ); fpuTest(); while (1); return 0; } Can someone help me investigate what could be wrong here? Could there be an issue in the FPU itself?
Cyclone 10 GX Nios V: TSE with mSGDMA Not Responding to Ping
Hello , I am using a Cyclone 10 GX with Nios V and the Micrium MicroC/OS-II operating system. My setup includes the Triple-Speed Ethernet Intel FPGA IP paired with the Modular Scatter-Gather DMA Intel FPGA IP, connected to a DP83620 PHY IC. Problem Description: In my implementation, the auto-negotiation completes successfully, and the link is established as indicated by the PHY status registers. I have configured an IPv4 address, subnet mask, and gateway using NetIPv4_CfgAddrAdd. Additionally, the socket() creation, bind(), and listen() calls in my socket server task all succeed without errors. However, the system does not respond to ping requests from a connected PC using the assigned IP address. Key Information: The Ethernet MAC and PHY configuration seem correct: Auto-negotiation and link establishment indicate that hardware connections are likely fine. The MAC and IP address settings are successfully applied. The Modular Scatter-Gather DMA is initialized and configured, but there might be a gap in how the RX/TX buffers and descriptors interact with the network stack. Debugging Steps Taken: Verified MAC, PHY, and DMA initialization logs. Confirmed that the socket(), bind(), and listen() functions in the SocketServerTask return no errors. Observed proper PHY register behavior, including link status and speed/duplex negotiation. If anyone has experience with a similar setup or can offer suggestions on how to debug further or resolve this issue, I would greatly appreciate your input!
Issue with SRAM and SDRAM in NiosV
Hey everyone. I am a student currently working on a project with niosv processor and de10 lite fpga. For this project i have Ashling Riscfree IDE to write the code. I currently have two designs and both of them cause errors related to SRAM in one and SDRAM Controller in another. In platform designer i had a design with IPs like niosv, jtag, sram, led_pio, uart_fifo. But then recently i added sdram controller and removed sram. Problems: 1) Both of the designs compile successfully in quartus but i get errors in Ashling IDE. In SRAM Version, I was getting errors that my .bss, .text and .rwdata segments weren't in the region of sram and also there was a memory overflow by around 30 KB. All these errors occurred while i was using printf function. I checked the linker script and all of those were linked with sram. So i guess thats correct. The thing is: Whenever i was doing minimal use of printf function without line breaker (\n) inside the printf function, i was getting those errors. And, also using many printf function (around 7-10) with the line breaker, also resulted the same errors. My Sram has 128 KB and should be enough for my program. 2) Having that problem i switched my design from sram to sdram controller. Here i have PLL100 for the clock generator and has phase shift of - 3ns to 3ns. Niosv, jtag, sdram conrroller, uart_fifo and led_pio are used in this design. The problem with this version is that i dont get error that i had with sram cause my space went up from 128KB to 64 MB, i guess. But another error has come up and that being, my simple hello world wont get printed properly. Whatever i print with or without line breaker (\n) with the printf function, only alternate characters get printed. For example, if i print "Hi Niosv", i get "iNov". Line space between the words is also counted as a character. Solution for either of these versions is acceptable, so i would really appreciate it, if you guys could give some tips or help to solve it. Thanks in advance guys.
