NIOS 2 for QSPI boot
Hello, We are trying to boot NIOS 2 processor from QSPI(EPCQ64ASI16N) on customized cyclone V board(HPS is not usable). As of now we are trying to perform a memory test on Nios2 processor, facing issues while testing qspi memory. Below is the memory test log, <----> Nios II Memory Test. <----> This software example tests the memory in your system to assure it is working properly. This test is destructive to the contents of the memory it tests. Assure the memory being tested does not contain the executable or data sections of this code or the exception address of the system. Press enter to continue or 'q' to quit. Base address to start memory test: (i.e. 0x800000) >0x800020 0x800020 End Address: >0xFFFFFE 0xFFFFFE Testing RAM from 0x800000 to 0xFFFFFE -Data bus test failed at bit 0x1 Press enter to continue or 'q' to quit. Base address to start memory test: (i.e. 0x800000) >0x1040020 0x1040020 End Address: >0x1060F73 0x1060F73 Testing RAM from 0x1040020 to 0x1060F73 -Data bus test passed -Address bus test passed -Byte and half-word access test passed -Testing each bit in memory device. Also find the linker script below, #ifndef __LINKER_H_ #define __LINKER_H_ /* * BSP controls alt_load() behavior in crt0. */ #define ALT_LOAD_EXPLICITLY_CONTROLLED /* * Base address and span (size in bytes) of each linker region */ #define EPCQ_CONTROLLER2_0_AVL_MEM_REGION_BASE 0x1800000 #define EPCQ_CONTROLLER2_0_AVL_MEM_REGION_SPAN 8388608 #define ONCHIP_MEMORY2_0_REGION_BASE 0x2040020 #define ONCHIP_MEMORY2_0_REGION_SPAN 135092 #define RESET_REGION_BASE 0x2040000 #define RESET_REGION_SPAN 32 /* * Devices associated with code sections */ #define ALT_EXCEPTIONS_DEVICE ONCHIP_MEMORY2_0 #define ALT_RESET_DEVICE ONCHIP_MEMORY2_0 #define ALT_RODATA_DEVICE ONCHIP_MEMORY2_0 #define ALT_RWDATA_DEVICE ONCHIP_MEMORY2_0 #define ALT_TEXT_DEVICE ONCHIP_MEMORY2_0 /* * Initialization code at the reset address is allowed (e.g. no external bootloader). */ #define ALT_ALLOW_CODE_AT_RESET /* * The alt_load() facility is called from crt0 to copy sections into RAM. */ #define ALT_LOAD_COPY_RWDATA #endif /* __LINKER_H_ */ Thanks, snehal_p
max10 remote system update nios with uart
hii i am trying to follow the application note to build a system to do a remote update of max10 over uart with nios 2 i built the qsys system with the on chip flash in order to store a factory and application rpd files i attached the image of the on chip flash configuration i configured it as a dual compressed image in order for the cfm sections to be available to store the files in the internal configuration under assignments-> device ->devices and pins -> configuration i choose dual compress image the same as on chip flash configuration also here i attached the image of my configuration but when i compile the design i get this error Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM that does not make sense to me cause i am using dual compressed image , i be glad for help or to see if i made a mistake in my configurations