Chainin and Chainout Ports in Arria 10 Native Fixed Point DSP IP Core Not Supported for m18x18_full Operation Mode.
Description When the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode, the chainin and chainout ports are visible to users. However, these ports are disabled internally in m18x18_full operation mode. If you connect the chainin and chainout ports when the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode, there will be no data transfer in and out to the DSP core. Resolution Leave the chainin and chainout ports unconnected when the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode. This issue will be fixed in a future version of the Quartus II software.Why does my synthesis fail on the floating-point library blocks?
Description Synthesis may fail with designs that include floating point library blocks. This issue affects all designs that use floating-point library blocks. The design fails. Resolution To work around the issue, perform the following steps: In the import directory that DSP Builder creates (DSPBuilder_<modelname>_import), when you compile (which fails), create a file called aaa_add.tcl (alphabetically first so it runs before other files). Add the following lines to that file: set quartus_dir $::env(QUARTUS_ROOTDIR) if [info exists ::env(DSPBA_HDL_DIR)] { set dspba_hdl_dir $::env(DSPBA_HDL_DIR) } else { set dspba_hdl_dir /dspba/Libraries } set_global_assignment -name VHDL_FILE /vhdl/fpc/hcc_package.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/math_package.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/hcc_implementation.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/math_implementation.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/fpc_library_package.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/fpc_library.vhd Create another file called aaa_add_msim.tcl. Add the following lines: set base_dir "<path to your DSPBA rtl directory>" set quartus_dir $::env(QUARTUS_ROOTDIR) if [info exists ::env(DSPBA_HDL_DIR)] { set dspba_hdl_dir $::env(DSPBA_HDL_DIR) } else { set dspba_hdl_dir /dspba/Libraries } file delete -force /fpc vlib fpc vmap fpc /fpc vcom -quiet -93 -work /fpc "/vhdl/fpc/hcc_package.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/math_package.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/hcc_implementation.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/math_implementation.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/fpc_library_package.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/fpc_library.vhd" Rerun the complation. This problem is fixed in DSP Builder v13.1.Build Command Not Functional for BSPs Created With the Nios II SBT
Description The build option in the Nios II IDE menu does not rebuild BSPs imported to the IDE. Resolution The Nios II SBT for Eclipse can both build and debug projects created on the command line. The Nios II SBT for Eclipse is the preferred tool for debugging Nios II SBT projects. For information about the Nios II SBT for Eclipse, refer to the Getting Started with the Graphical User Interface chapter of the Nios II Software Developer\'s Handbook. In the Nios II IDE, you can build the BSP by building the associated application project.Stratix V Hard IP for PCI Express IP Core Fails To Log First Error Pointer for Completion Timeout Error
Description The Stratix V Hard IP for PCI Express IP Core logs Completion Timeout errors in the Uncorrectable Error Status register, but does not log Completion Timeout errors in the Advanced Error Reporting (AER) Header Log Register or First Error Pointer field of the Advanced Error Capabilities and Control register as described in Section 7.10.7 of the PCI Express Base Specification Rev. 3.0. Resolution No workaround is available.EMIF Maximum Frequency Specification Update
Description This problem affects DDR2 and DDR3 products. DDR2 and DDR3 interfaces on Arria V GX/GT/SoC or Cyclone V and SoC devices may experience problems achieving timing closure at certain maximum frequencies. Resolution The workaround for this issue is to apply the appropriate solution for your configuration, as described below. (The stated performances apply to component topologies only; DDR2 DIMM configurations are not affected, and DDR3 DIMM configurations are not supported.) DDR2 SDRAM EMIF Maximum Frequency Specification Update for Arria V GX/GT/SoC or Cyclone V and SoC Devices For Arria V GX, -C5 speed grade device interfacing with a DDR2 SDRAM component with 2 chip selects using hard memory controller at 350 MHz: Upgrade the 400 MHz DDR2 SDRAM component to a 533 MHz DDR2 SDRAM component to achieve an interface frequency of 333 MHz. For Arria V GX, -C5 speed grade device interfacing with a DDR2 SDRAM component with 1 chip select using hard memory controller at 400 MHz: Upgrade the 400 MHz DDR2 SDRAM component to a 533 MHz DDR2 SDRAM component to achieve the specified maximum frequency. * If you experience timing failure with this configuration in version 13.0 SP1 DP5, file a service request to Altera. This specification is supported in version 13.1. For Arria V GX/GT, -I5 speed grade device interfacing with a DDR2 SDRAM component with 1 chip select using hard memory controller at 400 MHz: Upgrade the 400 MHz DDR2 SDRAM component to a 533 MHz DDR2 SDRAM component to achieve the specified maximum frequency. * If you experience timing failure with this configuration in version 13.0 SP1 DP5, file a service request to Altera. This specification is supported in version 13.1. DDR3/DDR3L SDRAM EMIF Maximum Frequency Specification Update for Arria V GX/GT/SoC or Cyclone V and SoC Devices For Cyclone V SoC (SE/SX), -A7 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using HPS hard memory controller at 400 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency. * If you experience timing failure with this configuration in version 13.0 SP1 DP5, file a service request to Altera. This specification is supported in version 13.1. For Cyclone V GX/E, -C6 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 2 chip selects using hard memory controller at 400 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency. For Cyclone V SoC (SE/SX/ST), -I7 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using HPS hard memory controller at 400 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency. For Arria V GX/GT, -I3 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using hard memory controller at 533 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency. For Arria V GX, -C4 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using hard memory controller at 533 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency. For Arria V GX, C5 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using either soft or hard memory controllers at 533 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency and avoid running memory interface at 425-449 MHz. For Arria V GX/GT, I5 speed grade device interfacing with a DDR3 or DDR3L SDRAM component, with 1 chip select using either soft or hard memory controllers at 533 MHz: Upgrade the 533 MHz DDR3 SDRAM component to a 667 MHz DDR3 SDRAM component to achieve the specified maximum frequency and avoid running memory interface at 420-449 MHz. This issue will not be fixed. The solutions for maximum frequency specifications have been updated in the External Memory Interface Spec Estimator.RapidIO II IP Core Might Send Truncated Data on Avalon-ST Pass-Through Interface if tt = 1
Description When the RapidIO II IP core sends data to the Avalon-ST Pass-Through interface in a transaction with Transport Type value 1, it truncates the payload to a multiple of eight bytes. Resolution This issue has no workaround. To avoid this issue, avoid sending payloads that are not a multiple of eight bytes in packets with ftype 9 and tt 1. This issue will be fixed in a future version of the RapidIO II MegaCore function for IP core variations with a 16-bit device ID. However, refer also to the erratum RapidIO II IP Core Does Not Support Streaming Data Packets With Device ID Width 16.Why can't QSPI flash be accessed using the Mailbox Client Intel® FPGA IP in designs that include HPS?
Description In Intel® Stratix® 10 and Intel Agilex® 7 devices with HPS, due to the implementation of HPS software, once the HPS is released from reset, you cannot access QSPI flash using the Mailbox Client Intel® FPGA IP. You will see error code 0x81 (QSPI_ALREADY_OPEN) for QSPI_OPEN operation (Please refer to Mailbox Client Intel® FPGA IP User Guide for the details of the operation command and error codes). Resolution This is expected behavior. In designs which include HPS, both SDM and HPS cannot access the shared QSPI flash simultaneously.Error: Error during execution of "{C:/altera/12.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Description You may experience the above error when generating a UniPHY-based memory controller. The error occurs because one of the system environment variables 'TEMP' points to a network drive and not a local drive. Resolution The workaround is to point the TEMP variable to the local machine, such as the C: drive. Also the variable HOMEDRIVE should point to the local machine.Why does active serial configuration fail when using an EPCS128 or quad-serial configuration (EPCQ) device?
Description Active Serial configuration may fail when using an EPCS128 or quad-serial configuration device (EPCQ) and a programming file which was generated using the Quartus® II software versions 13.0 and 13.0SP1. All EPCQ devices are affected (EPCQ16, EPCQ32, EPCQ64, EPCQ128, EPCQ256, and EPCQ512). This problem is caused by the file generation not automatically setting the Disable EPCS ID check option. Resolution To workaround this problem, check the Disable EPCS ID option when generating a programming file for the configuration device. This option is accessed by clicking the Advanced... button within the Convert Programming File utility. This problem is scheduled to be fixed in a future version of the Quartus II software.Why does OpenCL node locked license not work with multiple ethernet port?
Description The OpenCL node locked license are generated for specific physical address. The OpenCL node locked License also only works for the network interface named eth0. It doesn't work for hardware address eth1,2 or 3. Resolution It is recommended that only eth0 is used for OpenCL node locked licenses. This issue will be resolved in a future release of the Quartus II Software.