External I/O Channels Unavailable in Custom Platforms Ported from the Altera Stratix V Network Reference Platform
Description When designing your Custom Platform from the Stratix ® V Network Reference Platform (s5_net), if you perform the base revision compilation using a kernel that does not exercise all available I/O channels, all unused I/O channels will be excluded in the resulting kernel partition interface, and will be inaccessible to all subsequent board designs. Resolution When creating your Custom Platform from s5_net, perform all compilations using kernels that exercise all available I/O channels.Error: WDC_PCiScanDevices failed.
Description Attempting to configure a board with reprogram.exe might fail with the message: WDC_PCiScanDevices failed. Error 0x2000000f - Device not found Error opening the device This error might result from the following causes: The board is missing a default configuration image. The board does not finish configuring the FPGA until after the system enumerates all of its PCI Express® (PCIe®) devices. Resolution If the board is missing a default configuration image, update or change the default configuration image (also referred to as a programming file, .sof or .rbf). Refer to the board manufacturer\'s documentation for more information. If your board has been set up with a default programming file but does not appear in your operating system\'s list of devices, perform the following tasks: On the first system boot after the FPGA board has been powered down, perform a soft reboot (that is, reboot the host operating system without removing power to the PCIe devices). If a soft reboot does not resolve the problem and you have a system that allows you to configure the BIOS to increase the delay before the system performs PCIe device enumeration, set the delay to a higher value to provide more time for the board to configure the FPGA. If performing a soft reboot and increasing the delay value do not resolve the problem, most systems allow you to pause the boot sequence by entering the BIOS setup menu and then exit without saving changes. This pause gives the board enough time to configure the FPGA after power-up, and then restarts the boot sequence, re-enumerating the PCIe devices.Why does my synthesis fail on the floating-point library blocks?
Description Synthesis may fail with designs that include floating point library blocks. This issue affects all designs that use floating-point library blocks. The design fails. Resolution To work around the issue, perform the following steps: In the import directory that DSP Builder creates (DSPBuilder_<modelname>_import), when you compile (which fails), create a file called aaa_add.tcl (alphabetically first so it runs before other files). Add the following lines to that file: set quartus_dir $::env(QUARTUS_ROOTDIR) if [info exists ::env(DSPBA_HDL_DIR)] { set dspba_hdl_dir $::env(DSPBA_HDL_DIR) } else { set dspba_hdl_dir /dspba/Libraries } set_global_assignment -name VHDL_FILE /vhdl/fpc/hcc_package.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/math_package.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/hcc_implementation.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/math_implementation.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/fpc_library_package.vhd set_global_assignment -name VHDL_FILE /vhdl/fpc/fpc_library.vhd Create another file called aaa_add_msim.tcl. Add the following lines: set base_dir "<path to your DSPBA rtl directory>" set quartus_dir $::env(QUARTUS_ROOTDIR) if [info exists ::env(DSPBA_HDL_DIR)] { set dspba_hdl_dir $::env(DSPBA_HDL_DIR) } else { set dspba_hdl_dir /dspba/Libraries } file delete -force /fpc vlib fpc vmap fpc /fpc vcom -quiet -93 -work /fpc "/vhdl/fpc/hcc_package.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/math_package.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/hcc_implementation.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/math_implementation.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/fpc_library_package.vhd" vcom -quiet -93 -work /fpc "/vhdl/fpc/fpc_library.vhd" Rerun the complation. This problem is fixed in DSP Builder v13.1.Chainin and Chainout Ports in Arria 10 Native Fixed Point DSP IP Core Not Supported for m18x18_full Operation Mode.
Description When the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode, the chainin and chainout ports are visible to users. However, these ports are disabled internally in m18x18_full operation mode. If you connect the chainin and chainout ports when the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode, there will be no data transfer in and out to the DSP core. Resolution Leave the chainin and chainout ports unconnected when the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode. This issue will be fixed in a future version of the Quartus II software.Assign LVDS I/O standard-supported pins in right I/O banks of Arria V A1/A3/C3 devices as PLL clock input pins only
Description If you use the Quartus II software version 13.0 DP2 or 13.0 SP1 to create a design that targets an Arria V A1, A3 or C3 device, and you use the LVDS I/O standard-enabled pins in the right I/O bank for purposes other than as phase-locked loop (PLL) clock input pins, the resulting FPGA hardware might not function properly. Resolution You must assign the LVDS I/O standard-enabled pins in the right I/O bank as PLL clock input pins only. The Quartus II software version 13.0 DP2 or 13.0 SP1 does not issue an error message for incorrect assignments to these LVDS I/O standard-enabled pins.L2 Cache Controller Revision Incorrectly Listed as r3p2
Description The Cortex-A9 Microprocessor Unit Subsystem chapter in Volume 3: Hard Processor System Technical Reference Manual of the Arria V Device Handbook and the Cyclone V Device Handbook incorrectly reports the revision number of the ARM CoreLink Level 2 Cache Controller L2C-310. This chapter reports the L2 cache controller revision as r3p2. The actual revision number of the L2 cache controller in these devices is r3p3. Resolution Update to v14.0 or later of the handbook. If you are looking at an earlier handbook, disregard the listed revision number.Fatal Error: Read data comes back but dynamic OCT ctrl is not in read mode
Description You may see the following error when you simulate the UniPHY based DDR3 controller in full calibration mode. # ** Fatal: Read data comes back but dynamic OCT ctrl is not in read mode Resolution Open the following file in your simulation file-set: altdq_dqs2_ddio_3reg_<user_device>.sv Find the following line: (1, "Read data comes back but dynamic OCT ctrl is not in read mode"); Replace the line above with the following line: ("Read data comes back but dynamic OCT ctrl is not in read mode at time %f", ); The simulation should run without any errors once the above change is implemented.Error (178004): Could not find location for Clock Divider that enable routing of bonding clock lines
Description You may see the following Quartus® II Fitter error with Stratix® V GX and Arria® V GX devices if you attempt to place logical channel 0 of a bonded transceiver PHY IP on a transceiver channel that does not have access to a central clock divider block. "Error (178004): Could not find location for Clock Divider that enable routing of bonding clock lines" On Stratix V and Arria V transceiver devices, only physical channels 1 and 4 within a transceiver block can access a central clock divider. Resolution To work around this problem, assign logical channel 0 of the PHY IP to physical channel 1 or 4 of the transceiver bank. This information will be updated in a future version of the Altera Transceiver PHY IP Core User Guide. This limitation was removed in version 11.1.1 of the Quartus® II software.Wrong Decoding of MISC1 in DisplayPort Receiver
Description When used in lane 1 configurations, the DisplayPort IP core receiver may produce wrong MISC1 data as part of the received MSA. The logical state of the 3D video qualifier may also be wrong. This issue is fixed in version 14.1 of the DisplayPort IP core.NativeLink Simulation in UniPHY External Memory Interfaces fail for VHDL Output
Description In version 10.0 of the Quartus II software, when a user specifies VHDL output for the DDR2 and DDR3 SDRAM Controller with UniPHY, the QDR II and QDR II SRAM Controller with UniPHY, or the RLDRAM II Controller with UniPHY, and attempts to simulate using NativeLink, NativeLink fails and reports that it cannot find the file <design_name>.vho in the top-level directory. Resolution The workaround for this issue is to edit the <design_name>.vhd file and remove the line similar to the following: -- IPFS_FILES : <design_name>.vho.