error: Unexpected use of HDL library function(s) (possibly due to taking the address of the function)!
Description You may see this error message when the Intel® FPGA SDK for OpenCL™ compiler executes an EFI(Extensible Firmware Interface) function which is equivalent to its OpenCL funtion Resolution This problem is fixed beginning with the Intel FPGA SDK for OpenCL compiler software version 18.1.Why does aocl diagnose fail while using Windows 10?
Description When using Windows® 10, aocl diagnose may fail even though the board is installed in the PC and the user has installed the drivers using aocl install. If the user has installed the drivers then opens Windows Device Manager, the board should show up under "unknown device". Why does this happen? Windows 10 enforces driver signatures by default and the OpenCL drivers for our development kits are not "signed" for Windows 10. Resolution To work around this problem, run aocl uninstall then reboot the computer. After the computer has restarted, disable Windows 10 signed driver enforcement as shown below. Click the Start menu and select Settings. Click Update and Security. Click on Recovery. Click Restart now under Advanced Startup. (The computer won't actually restart until after step 8.) Click Troubleshoot. Click Advanced options. Click Startup Settings. Click on Restart. On the Startup Settings screen press 7 or F7 to disable driver signature enforcement. After the computer has finished booting up, run aocl install. Run aocl diagnose to verify that it succeeds Note: If your system has BitLocker enabled, you will need to enter the recovery key between steps 8 and 9 above. You must get the recovery key before starting the above procedure. To get the recovery key, do the following: Run Bitlocker Manager Select “Back up your Recovery Key” Select “Print the recovery key” This problem is scheduled to be fixed in a future version of Quartus.Why does #pragma ivdep not work correctly in aocl version 17.0?
Description In 16.1, this code behaved as expected where the outer loop was serialized due to dependencies and the inner loop dependencies were removed by the #pragma ivdep. // This loop gets serialized due to true dependencies with inner loop for (unsigned char x = 0; x < 4; x ) { // Inner loop does not have inter-iteration dependencies, but depends on outer loop #pragma ivdep for (unsigned char y = 0; y<64; y ) { In 17.0, the #pragma ivdep is now applied to both the inner and outer loop, so the dependencies in the outer loop are not accounted for by the compiler. As a result, similar code may not work correctly in hardware despite working in emulation. Resolution Workaround: 1. Add an extra argument "dummy" to the kernel. On the host side, always pass 1 for this dummy argument. BEFORE __kernel void my_kernel( __global cpx_t* restrict input, __global cpx_t* restrict result) AFTER __kernel void my_kernel( __global cpx_t* restrict input, __global cpx_t* restrict result, int dummy) 2. In the loop nest, wrap the inner loop in "if (dummy)": // This loop gets serialized due to true dependencies for (unsigned char x = 0; x < 4; x ) { if (dummy) { // No dependencies within each set of 64 iterations #pragma ivdep for (unsigned char y = 0; y<64; y ) { This issue is scheduled to be fixed in a future version of the Intel© OpenCL™ for FPGA SDK.Internal Compiler Error: Missing start cycle information for queried node: sync_out
Description You may see this error message when the Intel® FPGA SDK for OpenCL™ compiler executes an autorun kernel. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. Resolution This problem is fixed beginning with the Intel FPGA SDK for OpenCL compiler software version 18.0.Unable to unlock /intelFPGA_pro/17.1.1/hld/installed_packages
Description In version 17.1, installing the drivers for an OpenCL™ BSP can fail if the user does not have permisstion to write to the installation directory. (Due to a shared drive for example). The issue is that version 17.1 of the SDK for OpenCL now tries to write some files to the SDK installation directory during aocl install. Errors reported: touch: cannot touch '/intelFPGA_pro/17.1.1/hld/.inst_pkg_busy.marker': Permission denied Unable to unlock /intelFPGA_pro/17.1.1/hld/installed_packages Resolution In update 1, (version 17.1.1) the user can now set an environment variable to direct the installation script to save the files in a directory that the user has write permissions. >export AOCL_INSTALLED_PACKAGES_ROOT="/my_path/writeable_path/" >sudo aocl install or if the above commands do not work >sudo env AOCL_INSTALLED_PACKAGES_ROOT=/my_path/writeable_path/ aocl install Scheduled to be fixed in a future version of the SDK for OpenCL.L2 Cache Controller Revision Incorrectly Listed as r3p2
Description The Cortex-A9 Microprocessor Unit Subsystem chapter in Volume 3: Hard Processor System Technical Reference Manual of the Arria V Device Handbook and the Cyclone V Device Handbook incorrectly reports the revision number of the ARM CoreLink Level 2 Cache Controller L2C-310. This chapter reports the L2 cache controller revision as r3p2. The actual revision number of the L2 cache controller in these devices is r3p3. Resolution Update to v14.0 or later of the handbook. If you are looking at an earlier handbook, disregard the listed revision number.Why does my USB debug Master not work in the System console on the Cyclone® V GX FPGA development kit?
Description Due to a problem with the Cyclone® V GX FPGA Development Kit, when using the USB Debug Master core in Qsys, the System console does not discover the master device when you run the query get_service_paths master. Resolution To workaround this issue, the Intel® MAX® device on the board must be programmed with an updated image. Contact your local FAE to arrange for the board to be re-programmed.Is table below in Arria® V and Cyclone® V handbook DQ/DQS number for hard memory controller?
Description Arria® V: Table 7–2. Number of DQ/DQS Groups in Arria® V Devices per Side Cyclone® V: Table 6–2. Number of DQ/DQS Groups in Cyclone® V Devices per Side Resolution No. This table is only available for the soft memory controller. For the Hard Memory Controller DQ/DQS group, please refer to the device Pin-out files. The table for the Hard Memory Controller DQ/DQS group will be updated in a future handbook release.Why does MegaWizard report the multiplier output register option is no longer available when I upgrade my multiplier to Quartus 13.1?
Description The multiplier output register option is not available on 28nm ("V" series) devices. Resolution To resolve the error, disable the multiplier output register option and regenerate the core. If you wish to preserve the original latency introduced by the register, use the Pipelining tab to add a pipeline register with 1 clock latency. If an output register is desired, this can only be done for the adder output, on the Extra Modes tab.No 28nm Device Support for 10G Soft-XAUI Design Example
Description The 10G soft-XAUI design for the Stratix V PCI Express (PCIe) development kit is unable to complete the fitter process when the pin assignments at the high-speed mezzanine card (HSMC) Port A are using the transceiver channels 0, 2, 3, and 4. The 10G XAUI hardware design cannot be tested for the Stratix V SI development kit because the design is unable to interface with the external tester. The 10G XAUI design is unable to meet the timing analysis for the Cyclone V PCIe development kit in the Quartus software. This issue affects the 10G Ethernet 12.1 designs in the Cyclone V and Stratix V 28nm devices. Resolution There is no workaround for this issue. This issue will be fixed in a future ACDS release.