Can I connect VCCIO of I/O bank 1 to 2.5 V for AS configuration with EPCQ or EPCQA device when using Cyclone® III, Cyclone® IV, or Intel® Cyclone® 10 LP device?
Description No, when you use EPCQ or EPCQA quad-serial configuration device for AS configuration, you cannot connect VCCIO of I/O bank 1 to 2.5 V in Cyclone® III, Cyclone® IV, or Intel® Cyclone® 10 LP device. This is because the minimum VOH of the FPGA is insufficient for driving EPCQ or EPCQA input pins. Resolution Use 3.0 V or 3.3 V for Bank 1 VCCIO in Cyclone III, Cyclone IV, and Intel Cyclone 10 LP devices when AS configuration with EPCQ or EPCQA devices is used.Is there a known problem with the DATA[0] connection shown in the block diagrams for Passive Serial Configuration in the Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook?
Description Yes, in Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook version 2020.05.21 and earlier, there is a problem with the DATA[0] connection in the block diagram available in Chapter 6.1.2, Figures 88, 89 and 90. These diagrams incorrectly show a direct connection for DATA[0] between the Intel® Cyclone® 10 LP FPGA and Memory device. Resolution The DATA[0] pin should be connecting to the external host, such as a CPLD or microprocessor, as shown below. This is scheduled to be fixed in future release of the Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os HandbookWhere can I find the Cyclone 10 LP Passive Serial and Fast Passive Parallel configuration timing waveform and parameters?
Description You can refer to the Cyclone IV Device Handbook for the Cyclone IV E device Passive Serial and Fast Passive Parallel configuration timing waveform and parameters. The Cyclone® 10 LP device Passive Serial and Fast Passive Parallel configuration timing specification is following the Cyclone IV E device Passive Serial and Fast Passive Parallel configuration timing specification.How do I use the CHANGE_EDREG instruction to simulate a CRC error in Intel® Cyclone® 10 LP device?
Description You can perform CHANGE_EDREG using quartus_jli command with an appropriate JAM STAPL Format File (.jam) file in Intel® Cyclone® 10 LP device. You can download an example crc-edreg-c.jam. Here are the steps to execute quartus_jli command with the example .jam file Connect your PC to your Intel Cyclone 10 LP device through a download cable Configure your Intel Cyclone 10 LP device Open a command prompt when using Windows or a command shell when using Linux Execute the following command quartus_jli -c <cable number> -a CONFIG_IO crc-edreg-c.jam The cable number can be identified by using jtagconfig command. After CHANGE_EDREG is executed successfully, the 32-bit storage register of the error detection block is modified and a CRC error is detected.Can DCLK toggle from high to low any time before or during nSTATUS going high when using FPP and PS configuration schemes on Intel® Cyclone® 10 LP?
Description In the Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook Figure 102. "FPP Configuration Timing Waveform" and Figure 104. "PS Configuration Timing Waveform", there is a min time tST2CK spec for how long from nSTATUS going high until you are allowed the first rising edge on DCLK. This states that DCLK must be low for that minimum duration (tST2CK) before nSTATUS goes high. Resolution Prior to configuration, DCLK cannot toggle from low to high before nSTATUS is high. Once nSTATUS is high, DCLK must remain low for a minimum duration defined by the tST2CK specification. If DCLK is already in a high state prior to nSTATUS going high, it can transition from high to low provided the tST2CK specification is met.Error (292019): IP core 6AF7_0014 not supported in device family Cyclone 10 LP
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 17.1, you may see this errror when you compile NCO IP with a valid NCO IP license. Resolution A patch is available to fix this problem for the Quartus Prime Standard Edition software version 17.1. Download and install Patch 0.07std from the appropriate link below Download the Quartus Prime Standard Edition software version 17.1 Patch 0.07 for Windows (.exe) Download the Quartus Prime Standard Edition software version 17.1 Patch 0.07 for Linux (.run) Download the Readme for the Quartus Prime Standard Edition software version 17.1 Patch 0.07 (.txt) This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 18.0.Is there a syntax error when using the VHDL file of the ALTMULT_COMPLEX FPGA IP?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 and earlier, the VHDL file generated for the ALTMULT_COMPLEX FPGA IP, <ip_variation_name>.vhd, contains syntax errors. Using the generated IP files in the VHDL language is impossible. Resolution As a workaround, the user should generate the IP in Verilog HDL language.Why does .jic file programming of EPCQ-A devices fail when multiple Intel® Cyclone® 10 LP devices are in the same JTAG chain?
Description Due to a problem in the Intel® Quartus® Prime Software version 18.1, the programming of EPCQ-A devices is executed incorrectly with JTAG Indirect Configuration (.jic) file. You will see the failure when there are more than three Intel® Cyclone® 10 LP devices in a single JTAG chain, where each is connected to an EPCQ-A device as configuration flash. Resolution This problem was fixed in a recent version of the Intel® Quartus® Prime Software.Error (10228): Verilog HDL error at try_intel_generic_serial_flash_interface_top_1_qspi_inf_inst.sv(879): module "adapter_8_1" cannot be declared more than once.
Description Due to a problem in Intel® Quartus® Prime Pro Edition version 20.2 and earlier & Intel® Quartus® Prime Standard Edition version 20.1 and earlier, you may see the following synthesis error if there are 2 instances of Generic Serial Flash Interface Intel® FPGA IP. Error (10228): Verilog HDL error at try_intel_generic_serial_flash_interface_top_1_qspi_inf_inst.sv(879): module "adapter_8_1" cannot be declared more than once. Resolution To work around this problem, create a custom component in platform designer based on the HDL files generated by the IP. Modify names of modules that have naming conflicts, such as module "adapter_8_1". This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.3 and Intel® Quartus® Prime Standard Edition software version 21.1.Why does reconfiguration using MIF/HEX file on ALTPLL Intel® FPGA IP produce incorrect output clock frequency?
Description When generating an output clock frequency with C-counter exceeding 512, a post-scale counter cascading is implemented. If you are generating a MIF/HEX from the ALTPLL Intel® FPGA IP where the C-counter exceeds 512, cascaded C-counter is not supported. After reconfiguration, you may see that output clock frequency is incorrect. Resolution Enable Enter output clock parameters in the ALTPLL Intel® FPGA IP and manually adjust the output clock parameters. Ensure that the C-counter does not exceed the value of 512 and the internal setting isn't injecting post-scale counter cascading before generating the MIF/HEX file as shown in Figure 1. Figure 1. As an alternative, cascading of PLLs in normal or direct mode through the Global Clock (GCLK) network can be used to achieve the desired output clock frequency.
