Is there a syntax error when using the VHDL file of the ALTMULT_COMPLEX FPGA IP?

Description

Due to a problem in the Quartus® Prime Standard Edition Software version 22.1 and earlier, the VHDL file generated for the ALTMULT_COMPLEX FPGA IP, <ip_variation_name>.vhd, contains syntax errors.

Using the generated IP files in the VHDL language is impossible.

Resolution

As a workaround, the user should generate the IP in Verilog HDL language.