Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Warning (16817): Verilog HDL warning at altera_xcvr_*_reconfig_parameters.sv: overwriting previous definition of altera_xcvr_*_reconfig_parameters package
Description If your design contains multiple JESD204B IPs with different configurations, you may see the following warning in Intel® Quartus® Prime Pro software version 15.1 or later during Analysis and Synthesis stage. When targetting Intel Stratix® 10 devices: Warning (16817): Verilog HDL warning at altera_xcvr_rcfg_10_reconfig_parameters.sv: overwriting previous definition of module altera_xcvr_rcfg_10_reconfig_parameters When targetting Intel Arria® 10 or Intel Cyclone® 10 GX devices: Warning (16817): Verilog HDL warning at altera_xcvr_native_a10_reconfig_parameters.sv: overwriting previous definition of altera_xcvr_native_a10_reconfig_parameters package If your design does not rely on the *_reconfig_parameters.sv package files for performing transceiver reconfiguration, it is safe to ignore the warning. Resolution If your design must include the reconfiguration packages, ensure the uniqueness of each of the packages by renaming the packages. For example, a design that contains two simplex RX interfaces with different data rates, assign a unique name by changing the package module from: package altera_xcvr_native_a10_reconfig_parameters; To: package altera_xcvr_native_a10_reconfig_parameters_inst1; In the first instance of RX, and changing to another unique name: package altera_xcvr_native_a10_reconfig_parameters_inst2; In the second instance of RX. Then, import those packages into your design per your design requirements.Why is the input parallel termination value not shown in the Intel® Quartus® Prime fitter report for Input Pins and Bidirectional Pins?
Description Starting in the Intel® Quartus® Prime Pro Edition software version 19.3, input terminations using parallel OCT are reported in the Intel Quartus Prime Fitter > Plan Stage > Input Pins or Bidir Pins as Input Termination = ON. Previous Intel Quartus Prime Pro Edition software versions reported parallel OCT with the termination value. An example is Parallel 60 Ohm with Calibration. There is no workaround required as this is only a reporting issue. The parallel termination value is correctly set in the compiled project files with the value set in the Assignment Editor or in the case of EMIF IP as defined in the generated IP .qip file. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.When compiling an Intel® Cyclone® 10 FPGA design, why do I see the following Internal Error: Sub-system: FDI_DATA, File: /quartus/ddb/fdi/fdi_timing_model.cpp, Line: 753
Description Due to a problem with the Intel® Quartus® Prime Pro Edition Software v18.0, Intel® Cyclone® 10 GX FPGA designs might see the following Internal Error: Sub-system: FDI_DATA, File: /quartus/ddb/fdi/fdi_timing_model.cpp, Line: 753 during the fitter stage of compilation. This problem occurs when the Intel Cyclone 10 GX device family is installed without installing the Intel® Arria® 10 device family files. Resolution You are advised to install the Intel® FPGA Arria® 10 device family database file to work around this problem. This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 19.1.Why is my External Memory Interface (EMIF) IP preset file (.qprs) ignored after copying my project to a new location or using the Quartus® archiver?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and earlier, you might see that your .qprs file is not taken into account when reopening the External Memory Interface (EMIF) IP after copying your project to a new location or using the Quartus® archiver. This problem is caused by using an absolute path within the External Memory Interface (EMIF) IP .ip file. Resolution To correctly read in the .qprs file, browse to the new location of the .qprs file from within the Platform Designer. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.How accurate is the VCCBAT current reported in Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGA Early Power Estimator or Power Analyzer?
Description VCCBAT may draw higher current than the value estimated in the Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGA Early Power Estimator (EPE) or Power Analyzer, if you power off VCC when VCCBAT remains powered on. The maximum VCCBAT current could be up to 120 μA. Resolution If you use a battery to maintain volatile security keys when the system is not powered up, battery life may be shortened. Please contact your battery provider to evaluate the impact to the retention period of the battery used on your board. There is no impact if you connect the VCCBAT pins to the on-board power rail.Why is the IEEE 1588 PTP delay/offset measurement is inconsistent on 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP ?
Description Due to a problem with the Intel® Quartus® Prime Software version 21.2 and earlier, the gmii16b_rx_latency of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP output signal may potentially drift between 0 (min) and 0x3FFFFF (max) when Tx clock (tx_serial_clk), Rx clock (rx_cdr_refclk), link partner Tx data channel reference clock and recommended 80MHz latency_measure_clk of the IP core share a common clock source. As a result, the generated Rx timestamps are not accurate, and the measured delay/offset is much larger than expected in IEEE 1588 applications. However, the gmii16b_tx_latency signal is not impacted by this problem. This problem only impacts 1G and 2.5G IEEE 1588 operations. 5G and 10G IEEE 1588 operations are not affected. Resolution Modify IP core latency_measure_clk clock frequency from 80MHz to either 79.98MHz or 80.02MHz to avoid this problem. This modification can also be applied to the 80MHz sampling clock frequency of TOD Synchronizer Intel® FPGA IP and will not affect PTP timestamping accuracy. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.Why does simulation of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* example design testbench not include a DMA process?
Description Due to a problem with the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* example design testbench DMA transactions are not processed. Resolution In current versions of the Intel® Quartus® Prime Design Software, to correctly simulate DMA processes, modify the 'apps_type_hwtcl' parameter from '3' to '6' within the 'altpcie_a10_tbed_hwtcl' module instantiation in the file 'dut_pcie_tb_ip.v'. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4.Error: The Maximum channels supported is 8 for LVDS variant Or Error: “Number of channels” (NUM_CHANNELS) 12 is out of range: 1-11
Description You may receive the above error message when selecting the port number greater than eight and the transceiver type as LVDS I/O for Triple Speed Ethernet IP Core in Quartus® Prime Software version 17.0.2, including patch 2.05 or Quartus® Prime Software version 17.1. Resolution The Triple Speed Ethernet IP with LVDS I/O interface can only support up to 8 ports. Therefore, a port number larger than 8 is not a valid option, and those options will be removed in a future version of Quartus® Prime Software. This is already fixed in Quartus® Prime version 17.1.How can I modify the Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* Design Example Testbench to include custom transactions?
Description Whilst not supported by Altera, the Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* Design Example Testbench is in clear text RTL and can be modified to include simple additional transactions. The testbench and Root Port BFM or Endpoint BFM provide a simple method to do basic testing of the Application Layer logic that interfaces to the variation. This BFM allows you to create and run simple task stimuli with configurable parameters to exercise basic functionality of the example design. The testbench and BFM are not intended to be a substitute for a full verification environment. Corner cases and certain traffic profile stimuli are not covered. Refer to the items listed below for further details. To ensure the best verification coverage possible, Atlera strongly suggests that you obtain commercially available PCI Express verification IP and tools, or do your own extensive hardware testing, or both. The Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide section 13.1. Avalon-MM Endpoint Testbench incorrectly states that the file altpcietb_bfm_rp_gen3_x8.sv should be the module used to modify and vary the transactions sent to the example endpoint design or your own design. Resolution To modify and vary the transactions sent to the example endpoint design or your own design, please refer to section 13.3. Avalon-MM Test Driver Module of the Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide. Due to an update to the IP Core, the correct filename to be modified has changed from altpcietb_bfm_driver_avmm.v, as stated in the documentation, to altpcietb_bfm_driver_downstream.v. The information in the Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide has been updated to reflect this change.