Why doesn't the Triple-Speed Ethernet (TSE) FPGA IP for all devices always maintain a negative running disparity during idle cycles as per the IEEE 802.3 standard?
Description Due to a problem in the Quartus® Prime Pro Edition software, when using the Triple-Speed Ethernet (TSE) FPGA IP across supported device families, the transmitter may not maintain a negative running disparity during idle cycles as defined in the IEEE 802.3 standard. Specifically, the first IDLE sequence after a packet or configuration set is not always generated as /I1/, which is required to restore the running disparity to negative. Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition software version 24.1 for Agilex™ 7 FPGA F-Series E-Tile devices. Download version 24.1 patch 0.47 for Windows and Linux below This patch ensures the transmitter maintains negative running disparity for Agilex™ 7 FPGA F-Series E-Tile devices by inserting the first idle sequence (/I1/) whenever required, followed by all subsequent idle sequences (/I2/), maintaining compliance with the IEEE 802.3 standard. Please contact your local Sales representative or submit a request through the Support page for further support. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Unable to unlock /intelFPGA_pro/17.1.1/hld/installed_packages
Description In version 17.1, installing the drivers for an OpenCL™ BSP can fail if the user does not have permisstion to write to the installation directory. (Due to a shared drive for example). The issue is that version 17.1 of the SDK for OpenCL now tries to write some files to the SDK installation directory during aocl install. Errors reported: touch: cannot touch '/intelFPGA_pro/17.1.1/hld/.inst_pkg_busy.marker': Permission denied Unable to unlock /intelFPGA_pro/17.1.1/hld/installed_packages Resolution In update 1, (version 17.1.1) the user can now set an environment variable to direct the installation script to save the files in a directory that the user has write permissions. >export AOCL_INSTALLED_PACKAGES_ROOT="/my_path/writeable_path/" >sudo aocl install or if the above commands do not work >sudo env AOCL_INSTALLED_PACKAGES_ROOT=/my_path/writeable_path/ aocl install Scheduled to be fixed in a future version of the SDK for OpenCL.Creating OTN_cascade or SDI_cascade Instances at a Low or Medium IP Bandwith Causes the Arria® 10 and Cyclone® 10 GX fPLL or ATX PLL IP Parameter Editor GUI to Encounter an Error Related to f_max_pfd
Description If you set the fPLL or ATX PLL IP bandwidth to low or medium for Arria® 10 and Cyclone® 10 GX devices while attempting to create OTN_cascade or SDI_cascade instances, the IP Parameter GUI might display an error that relates to f_max_pfd. This issue affects the Quartus® Prime Standard Edition Software and the Quartus® Prime Pro Edition Software. Resolution In the fPLL or ATX PLL IP Parameter Editor, you cannot select the bandwidth after you select the OTN or SDI protocol. Therefore, before you create OTN_cascade or SDI_cascade instances, first select Basic from the Protocol mode pull-down menu and then select High from the Bandwith pull-down menu.Arria 10 and Cyclone 10 GX EMIF Simulations May Fail with Certain Versions of Riviera-PRO
Description This problem affects all external memory protocols on Arria® 10 and Cyclone® 10 devices. In the Quartus Prime software version 14.0, simulations using the Aldec Riviera-PRO simulator will fail for Riviera-PRO versions older than 2014.10. Resolution The workaround for this issue is to simulate with Riviera-PRO version 2014.10 or later. (Aldec case ID SPT69955)Why does the JESD204B Intel® FPGA IP Example Design fail to operate correctly when using the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices?
Description Due to a known problem in the Intel® Quartus® Prime Pro software versions 19.1 to 19.4, the JESD204B Intel® FPGA IP Example Design may fail to operate correctly when using the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. This is due to 2 missing ports if synthesising and 1 missing port if simulating the JESD204B Intel® FPGA IP Example Design. Resolution To work around this problem, follow the steps below: 1. For example design synthesis, add these two ports into "altera_jesd204_ed_RX_TX.sv" located at "//ed_synth" at line 365. { .jtag_avmm_bridge_master_reset_reset (jtag_avmm_rst), .jtag_reset_in_reset_reset_n (1'b1), } 2. For example design simulation, add this port at line 364 into "altera_jesd204_ed_RX_TX.sv" located at "//ed_sim/testbench/models" at line 365. { .jtag_reset_in_reset_reset_n (1'b1), } This problem is fixed starting from the Intel® Quartus® Prime Pro Edition software version 20.1.Why am I unable to set the 'Size of address pages' to a value between 17 and 21 bits for the Intel® Arria® 10 FPGA and Intel® Cyclone® 10 GX FPGA Hard IP for PCI Express in Avalon® memory-mapped mode?
Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 18.1 and later, address page sizes between 17 and 21 bits (inclusive) are not available for selection when using the Intel® Arria® 10 FPGA and Intel® Cyclone® 10 GX FPGA Hard IP for PCI Express in Avalon® memory-mapped mode with Avalon memory-mapped address width of 32 bits. Resolution This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 22.1.Why does the Intel® Arria® 10 and the Intel® Cyclone® 10 Avalon®-ST or Avalon® -MM Interface for PCI Express* IP example design report ignored SDC constraint warnings?
Description When compiling the Intel® Arria® 10 or the Intel® Cyclone® 10 Avalon®-ST or Avalon® -MM Interface for PCI Express* IP example design generated using Intel® Quartus® Prime Software version 19.4 or earlier, the following ignored SDC constraint warnings will be seen. Warning(332174): Ignored filter at altera_xcvr_native_a10_false_paths.sdc(63): *twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_10g_krfec_tx_pld_rst_n could not be matched with a pin Warning(332174): Ignored filter at altera_xcvr_native_a10_false_paths.sdc(53): *twentynm_xcvr_native_inst|*inst_twentynm_pcs|*twentynm_hssi_*_pld_pcs_interface*|pld_pmaif_tx_pld_rst_n could not be matched with a pin Warning(332049): Ignored set_max_skew at altera_pci_express.sdc(34): Argument -to with value [get_registers {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_data_reg[*] *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_datak_reg[*]}] contains zero elements Warning(332049): Ignored set_max_skew at altera_pci_express.sdc(35): Argument -to with value [get_registers {*|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_data_reg_1[*] *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|dbg_rx_datak_reg_1[*]}] contains zero elements Warning(332049): Ignored set_max_delay at altera_pci_express.sdc(37): Argument is an empty collection Warning(332174): Ignored filter at altera_pci_express.sdc(38): *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_sc_bitsync_node:rx_polinv_dbg.dbg_rx_valid_altpcie_sc_bitsync_1|altpcie_sc_bitsync:altpcie_sc_bitsync|altpcie_sc_bitsync_meta_dff[0] could not be matched with a clock or keeper or register or port or pin or cell or partition Warning(332049): Ignored set_false_path at altera_pci_express.sdc(38): Argument is not an object ID Warning(332174): Ignored filter at altera_pci_express.sdc(39): *|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_sc_bitsync_node:rx_polinv_dbg.dbg_rx_valid_altpcie_sc_bitsync|altpcie_sc_bitsync:altpcie_sc_bitsync|altpcie_sc_bitsync_meta_dff[0] could not be matched with a clock or keeper or register or port or pin or cell or partition Warning(332049): Ignored set_false_path at altera_pci_express.sdc(39): Argument is not an object ID These SDC constraint warnings can be ignored. Resolution User can safely ignore these SDC constraint warningsIs the I/O delay feature supported for LVDS, RSDS, mini-LVDS, and LVPECL I/O standards when using Intel® Arria® 10 and Intel® Cyclone® 10 GX devices?
Description Due to a problem in Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook and Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook, Table 49 of Intel® Arria® 10 Programmable IOE Features I/O Buffer Types and I/O Standards Support, and Table 39 of Intel Cyclone 10 GX Programmable IOE Features I/O Standards and Buffer Types Support, don't include LVDS, RSDS, mini-LVDS and LVPECL I/O standards. These IO standards all support the I/O Delay feature. Resolution This problem is currently scheduled to be fixed in a future release of Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook and Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook.Critical Warning (332049): Ignored create_generated_clock at altera_emr_unloader.sdc(14): Argument <targets> is an empty collection
Description Due to a problem in the Quartus® Prime Standard Edition Software version 22.1, you might see this critical warning when using the Error Message Register Unloader IP. You will also see an unconstrained clock reported in the Unconstrained Paths Report in the Timing Analyzer, as shown below, when using the Error Message Register Unloader IP. This is due to the constraint in altera_emr_unloader.sdc, which failed to address this issue. *|altera_emr_unloader:emr_unloader_component|current_state.STATE_CLOCKHIGH Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 22.1, follow these steps: In the altera_emr_unloader.sdc file, comment out line 14. Add the create_generated_clock constraint to the altera_emr_unloader.sdc file. For example: create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_pins {*|alt_fault_injection_component|alt_fi_inst|*oscillator|clkout}] [get_keepers { *|emr_unloader_component|current_state.STATE_CLOCKHIGH}] This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.