CXL Adoption Ramps with New Product Announcements from Intel and Others
Enthusiasm over Artificial Intelligence (AI) related products, such as the generative AI software ChatGPT, is igniting another wave of demand for high-performance computing, and a return to typical growth patterns in data center infrastructure, cloud computing, and high-performance computing (HPC) segments.
CXL type 3 example design increase to 128GB per channel?
What needs to change in the CXL type 3 example design to increase the Memory to 128GB per channel? I tried changing the emif IP to a DIMM, and updated the scripts to not define ENABLE_DDR_DBI_PINS. I updated the pinouts. But I get: Error(129015): Output port DATA_OUT on atom "ed_top_wrapper_typ3_inst|MC_CHANNEL_INST[0].mc_top|GEN_CHAN_COUNT_EMIF[0].emif_inst|emif|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].lane_gen[2].lane_inst|lane_inst", which is a tennm_io_12_lane primitive, is not legally connected and/or configured Info(129016): Output port DATA_OUT[8] is disconnected, but the Compiler expects this output port to be connected Any idea what I am missing?