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Is the Figure 55 of Credit Limit Update on Transmit Flow Control Credit Interface in the GTS AXI Streaming IP for PCI Express* User Guide correct?
Description In Figure 55 of the GTS AXI Streaming IP for PCI Express* User Guide version 24.3, you might see p<n>_ss_app_st_txcrdt_tdata[18:0] signal shows 'hFFF in cycle 9. The correct v...108Views0likes0CommentsPCI Express User Guide Incorrectly Shows Support for Avalon-MM Interface in Multiple Device Families
Description Table 1-9 in the PCI Express Compiler User Guide incorrectly shows support for an Avalon-MM interface in variations that target the Cyclone II, Cyclone III, Stratix II, and Stratix III d...12Views0likes0CommentsWhy do the BSEL/CSEL pull-up and pull-down resistor values in Cyclone® V Device Schematic Review Worksheet not match with the Cyclone® V Device Family Pin Connection Guidelines?
...nformation in the Cyclone® V Device Family Pin Connection Guidelines version 2.6 which recommends connecting a pull-up such as 10-kΩ or pull-down resistor such as 1-kΩ to select t...170Views0likes0CommentsIncorrect Definition of npor Reset in the Stratix V Hard IP for PCI Express User Guide
Description The Stratix V Hard IP for PCI Express User Guide define npor as an active high reset signal; however, npor is active low. Resolution No workaround is required. This issue is fixed i...146Views0likes0CommentsIP Compiler for PCI Express User Guide Does Not Include Pin Assignments in Qsys Design Example
...he Qsys design example in the IP Compiler for PCI Express User Guide do not describe this step. If you skip this step, the Qsys design example does not compile with the required pin assignments. I...263Views0likes0CommentsPCI Express User Guide and Parameter Editor Allow Incorrect Application Clock Frequency for Stratix V GX Devices
...ompiler User Guide incorrectly indicates that this clock can also have frequency 62.5 MHz, and the PCI Express parameter editor allows the selection of 62.5 MHz or 125 MHz for this clock. All Gen1 × PCI Express...127Views0likes0Comments