86 Results
Is the Figure 55 of Credit Limit Update on Transmit Flow Control Credit Interface in the GTS AXI Streaming IP for PCI Express* User Guide correct?
Description In Figure 55 of the GTS AXI Streaming IP for PCI Express* User Guide version 24.3, you might see p<n>_ss_app_st_txcrdt_tdata[18:0] signal shows 'hFFF in cycle 9. The correct v...81Views0likes0CommentsPCI Express User Guide Incorrectly Shows Support for Avalon-MM Interface in Multiple Device Families
Description Table 1-9 in the PCI Express Compiler User Guide incorrectly shows support for an Avalon-MM interface in variations that target the Cyclone II, Cyclone III, Stratix II, and Stratix III d...7Views0likes0CommentsIncorrect Definition of npor Reset in the Stratix V Hard IP for PCI Express User Guide
Description The Stratix V Hard IP for PCI Express User Guide define npor as an active high reset signal; however, npor is active low. Resolution No workaround is required. This issue is fixed i...95Views0likes0CommentsPCI Express User Guide and Parameter Editor Allow Incorrect Application Clock Frequency for Stratix V GX Devices
...ompiler User Guide incorrectly indicates that this clock can also have frequency 62.5 MHz, and the PCI Express parameter editor allows the selection of 62.5 MHz or 125 MHz for this clock. All Gen1 × PCI Express...96Views0likes0CommentsIP Compiler for PCI Express User Guide Does Not Document derr_cor_ext_rcv Signal as a Debug Signal
Description The IP Compiler for PCI Express User Guide does not document the fact that the derr_cor_ext_rcv[1:0] signals are debug signals. These signals do not affect the operation of the IP C...85Views0likes0Comments