90 Results
Is the Figure 55 of Credit Limit Update on Transmit Flow Control Credit Interface in the GTS AXI Streaming IP for PCI Express* User Guide correct?
Description In Figure 55 of the GTS AXI Streaming IP for PCI Express* User Guide version 24.3, you might see p<n>_ss_app_st_txcrdt_tdata[18:0] signal shows 'hFFF in cycle 9. The correct v...49Views0likes0CommentsPCI Express User Guide Incorrectly Shows Support for Avalon-MM Interface in Multiple Device Families
Description Table 1-9 in the PCI Express Compiler User Guide incorrectly shows support for an Avalon-MM interface in variations that target the Cyclone II, Cyclone III, Stratix II, and Stratix III d...3Views0likes0CommentsWhy am I seeing the below mask error for R-Tile Avalon® Streaming FPGA IP for PCI Express Gen4 (16GT/s) when running the Lane Margining tool in Debug Toolkit?
...6.0GT/s). These data are scheduled to be updated in a future release of Quartus® Prime Pro Edition software version and R-Tile Avalon® Streaming IP for PCI Express User Guide. Note: The m...32Views0likes0CommentsIncorrect Definition of npor Reset in the Stratix V Hard IP for PCI Express User Guide
Description The Stratix V Hard IP for PCI Express User Guide define npor as an active high reset signal; however, npor is active low. Resolution No workaround is required. This issue is fixed i...55Views0likes0Comments