Why is the Read Device Dummy Clock instruction unreliable when using the QUAD and DUAL I/O options on the ASMI Parallel Intel® FPGA IP?

Description

When the  read_dummyclk input of the ASMI Parallel Intel® FPGA IP is asserted, the IP performs a read of the non-volatile control register of the EPCQ configuration device to determine the number of dummy cycles that are required for a fast read operation.

Due to a problem with the IP, the outputs of the FPGA are not tri-stated during the read status operation at the time when the EPCQ device should return the data.  This leads to a conflict on the DATA[3..0] signals.  This conflict may mean that the incorrect value is returned.

Resolution

Do not use the DUAL or QUAD I/O options available on the ASMI Parallel Intel® FPGA IP.

This problem has been resolved in the the Quartus® II software version 14.0 and onwards.

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