Why is data packet loss due to CRC error observed in Agilex™ 5 and Agilex™ 3 TSN XCVR SGMII 1G mode?

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.1, when running the TSN - SGMII XCVR System for the Agilex™ 5 FPGA E-Series Premium Development Kit, you may observe data packet loss in the TX direction for a 1G SGMII configuration with the TSN transceiver PHY. This issue is not seen with 10m,100m, and 2.5G configurations.

Resolution

To work around this problem, some changes in the software and hardware design files are required.

Software Changes:

1. Change link.speed1000 parameter value from XGMAC_CONFIG_SS_1000_GMII to XGMAC_CONFIG_SS_2500_GMII in the following file.
<user_path>/src/sw/agilex5_dk_a5e065bb32aes1-gsrd-rootfs/tmp/work-shared/agilex5_dk_a5e065bb32aes1/kernel-source/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

mac->link.speed10 = XGMAC_CONFIG_SS_10_MII;

mac->link.speed100 = XGMAC_CONFIG_SS_100_MII;

-mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII;

+mac->link.speed1000 = XGMAC_CONFIG_SS_2500_GMII;

mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII;

 

Hardware Design Changes:

1. Replace the existing input with 2'b00 for the signals below in the file below:
<user_path>/applications.fpga.soc.agilex5e-ed-tsn-config3/src/hw/ghrd_agilex5_top.v

.phy_0_gmii8b_mac_speed_export (2'b00),

...

.phy_0_xcvr_mode_export (2'b00),

Additional Information

This issue is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.