Why I can’t place Intel® Stratix® 10 partitions adjacent to Transceiver Bank, export and reuse in another project?

Description

Due to a problem in Intel® Quartus® Prime Pro Edition Software version 18.0 or earlier, when a partition is placed in a row clock region adjacent to the Transceiver Bank in one project (or in a developer project) and is reused using the QDB_FILE_PARTITION assignment into another project (or into consumer project), you may see the following Internal Error:

Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/altera_arch_common/altera_arch_re_network_routing_constraints.cpp

• A clock sector is defined by the green box in Figure. 1
• A row clock region is half-clock sector-wide, and one LAB row tall represented by the red dotted box in Figure. 1.
  • In the consumer project, if the reused partition has a placement in this region, you may see the above Internal Error.

Resolution

To work around this problem, use logic lock regions in the developer project to avoid placing the partition in the row clock region adjacent to the Transceiver Bank.

• In the developer project, use logic lock region constraints to restrict the placement of the partition to be exported to half clock sector away from the Transceiver Bank (constrain outside the highlighted yellow region). Compile and export the partition at the final stage.
• When reused in the consumer project, the exported partition will maintain the placement defined in the developer project.

This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro Edition Software.

Why can't I compile Intel® Stratix® 10 partitions exported from another project with a different top-level?

Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp

Internal Error: Sub-system: LALE, File: /quartus/legality/lale/lale_new_solver.cpp

Why can’t I place Intel® Stratix® 10 partitions adjacent to the I/O Bank of EMIF/PHY Lite/LVDS Interfaces, export, and reuse in another project?