Why doesn’t the MAX® 10 DDR2 mem_odt signal toggle during calibration in both the RTL simulation and in hardware operation?

Description

Due to a problem with the MAX® 10 DDR2 IP, the mem_odt signal doesn’t toggle during calibration. Although this is incorrect behavior for the mem_odt signal during calibration, there is no functional impact to the DDR2 interface.

After calibration, the mem_odt signal toggles as expected during memory write transactions.

Resolution

This problem is scheduled to be fixed in the Quartus® Prime Standard version 19.1.