Why does using MIPI DSI-2 Fixed Latency Mode with Separate Clock Domains cause instability in the Quartus® Prime Pro Edition software version 25.3?

Description

Due to a problem in the Quartus® Prime Pro Edition software version 25.3, the MIPI DSI-2 FPGA IP core prevents Fixed Latency Mode from being automatically disabled when Separate Clock Domains are selected. This can result in uncontrolled clock crossings, hardware instability, timing violations, and possible design failures.  
Fixed Latency Mode is intended only for use with Common Video Input and MIPI Clocks enabled, which ensures operation within a single synchronous clock domain.

Resolution

If you disable Common Video Input and MIPI Clocks, manually disable Fixed Latency Mode to avoid instability.
This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.