Why does the SYNC_N signal keep asserting when using the JESD204B IP design example in Intel® Stratix® 10, Intel® Arria® 10, or Intel® Cyclone® 10 GX devices?

Description

Due to a problem in Intel® Quartus® Prime Standard/Prime Pro Edition Software v18.0 and earlier, the SYNC_N signal may assert unexpectedly when using the JESD204B IP design example in Intel® Stratix® 10, Intel® Arria® 10, or Intel® Cyclone® 10 GX devices.

This is because, in the JESD204B design example, the sysref signal is sampled through software (NIOS/System Console) in the mgmt_clk domain, which is asynchronous to the IP core domain link_clk. The IP core operation is rising edge sensitive to sysref pulse. The asynchronous sysref signal may cause its rising edge to go undetected in the link_clk domain.

Resolution

To work around this, synchronize the sysref signal to the link_clk domain in the top wrapper of the JESD204B IP design example. (altera_jesd204_ed_RX/TX/RX_TX).

This problem is fixed starting from the Intel® Quartus® Prime Standard/Pro Edition Software versions 18.1.