Why does the Stratix® 10 FPGA Hard IP for PCI Express, configured in Gen3 mode, enter Recovery state several times when changing speed to Gen3?

Description

The Stratix® 10 L-Tile Hard IP for PCI Express* core configured in Gen3 mode may undergo several Recovery cycles when changing speed to Gen3.  After a few Recovery cycles, the link stabilizes in the L0 state.  Initial link-up to Gen3 is not affected. The Recovery cycles only occur in subsequent speed changes after initial link training to Gen3.

Resolution

This issue is not fixed in L-Tile.