Why does the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express VirtIO configuration register access return unexpected result when multiple physical function or SR-IOV is enabled ?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 and 21.4, you might see that the Configuration Write or Read to P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express VirtIO configuration space register return unexpected result when the following Hard IP Mode is selected:

• Gen4x16, Interface - 512-bit   (PLD Clock Frequency: 175/200/225/250 MHz)
• Gen4x8, Interface - 512-bit     (PLD Clock Frequency: 175/200/225/250 MHz)
• Gen4x8, Interface - 256-bit     (PLD Clock Frequency : 175/200/225/250 MHz)

Resolution

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.1.