Why does the mgmt_waitrequest signal from the IOPLL Reconfig Intel FPGA not behave as expected when performing Dynamic Phase Shift in Intel® Stratix® 10 FPGA and Intel Agilex® 7 devices?

Description

Due to a known problem in Intel® Quartus® Prime Pro Edition Software version 19.4 and earlier, the mgmt_waitrequest signal output from the IOPLL Reconfig Intel FPGA in Intel Stratix® 10 devices and Intel Agilex® 7 devices will operate in the opposite way that is described in the Intel® Stratix® 10 Clocking and PLL User Guide and Intel Agilex® Clocking and PLL User Guide by deasserting when Dynamic Phase Shift (DPS) is requested and asserting once completed.

Resolution

This problem is fixed starting with Intel® Quartus® Prime Pro Edition Software version 20.2.