Why does the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example fail in compilation?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example generated using preset 10GBase-R Example Design fails to compile with the error message as shown below.

Error: Error opening /alt_em10g32_0_EXAMPLE_DESIGN/LL10G_10GBASER/rtl/address_dec/ip/address_dec/address_dec_merlin_mstr_trans_0.ip. 
 

Resolution

This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.3.