Why does the Intel® Stratix®10 Hard IP for PCIe* report incorrect link widths?

Description

Due to an encoding problem with the link acknowledge logic in Intel® Stratix® 10 H-Tile ES2 devices, link widths will be incorrectly acknowledged as shown below:

Actual Link Width	Link Acknowledge
x1	x16
x2	x1
x4	x2
x8	x4
x16	x8

Resolution

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Edition Software.