Why does the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Hard IP not use the parity bytes from the Avalon® Streaming TX Interface?

Description

The Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Hard IP automatically generates the byte parity for the data bus parity protection feature. The parity bytes provided on the below signals will not be used by the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Hard IP for the data bus parity protection feature.

 

Signals name:

tx_st_data_par_i

tx_st_hdr_par_i 

tx_st_tlp_prfx_par

Resolution

This information is included in the 21.4 release of the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* User Guide